Boot Mode; Jtag - Enclustra Mars XU3 User Manual

Figure 14: Power-on Reset Delay Override (PORSEL) Resistors - Assembly Drawing Bottom View (upper middle part)
For details on the POR_OVERRIDE signal please refer to the Zynq UltraScale+ MPSoC Technical Reference
Manual [19].
3.4

Boot Mode

The boot mode can be selected via two signals available on the module connector.
Table 30 describes the available boot modes on the Mars XU3 SoC module.
BOOT BOOT
MODE1 MODE0
0 0
0 1
1 0
1 1
Table 30: Boot Modes
3.5

JTAG

The Zynq Ultrascale+ devices include two separate JTAG controllers: the Zynq Ultrascale+ TAP and the ARM
DAP. The first one uses the PS dedicated JTAG pins and has access to both PS and PL and the second one
uses the PS PJTAG pins and is used for loading programs, system test, and PS debug.
D-0000-432-001
Mode Description
Straps [3:0]
0110 Boot from eMMC flash
1110 Boot from SD card (with an ex-
ternal SD 3.0 compliant level
shifter;
VCC_CFG_MIO is 1.8 V)
0010 Boot from QSPI flash
0101 Boot from SD card (default
mode)
only available when
39 / 52
Remarks
-
Not supported (may be sup-
ported in the future)
-
-
Version 04, 25.07.2019