Pull-Up During Configuration; Pull-Up During Configuration (Pudc) - Enclustra Mars XU3 User Manual

Warning!
All configuration signals except for BOOT_MODE must be high impedance as soon as the device is
released from reset. Violating this rule may damage the equipped MPSoC device, as well as other
devices on the Mars XU3 SoC module.
3.2

Pull-Up During Configuration

The Pull-Up During Configuration signal (PUDC) is pulled to GND on the module; as PUDC is an active-low
signal, all FPGA I/Os will have the internal pull-up resistors enabled during device configuration.
If the application requires the pull-up during configuration to be disabled, this can be achieved by removing
R204 component and by mounting R203 - in this configuration the PUDC pin is connected to 1.8 V.
Figure 11 illustrates the configuration of the I/O signals during power-up. Figure 12 indicates the location of
the pull-up/pull-down resistors on the module PCB - upper middle part on the bottom view drawing.
Figure 11: Pull-Up During Configuration (PUDC)
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