Usb 2.0; Usb Phy Type; Signal Description; Usb 3.0 - Enclustra Mars XU3 User Manual

PHY Register Name
RXD0-RXD3
RX_DV
RX_CLK
TXD0-TXD3
TX_EN
GTX_CLK
Table 26: Gigabit Ethernet PHYs Configuration - RGMII Delays
2.20

USB 2.0

The Mars XU3 SoC module has an on-board USB 2.0 PHY connected to the MPSoC device, to the PS to I/O
bank 502. The USB interface can be configured for USB host, USB device and USB On-The-Go (host and
device capable) operations.
2.20.1

USB PHY Type

Table 27 describes the equipped USB PHY device type on the Mars XU3 SoC module.
PHY Type
USB3320C
Table 27: USB 2.0 PHY Type
2.20.2

Signal Description

The ULPI interface is connected to MIO pins 52-63 for use with the integrated USB controller.
Warning!
When generating the FSBL in certain SDK versions the power management of the USB interface is not
done properly, causing the USB interface not to work as expected. A patch to psu_init.c file fixing this
issue (required for SDK 2017.4) is available upon request.
2.21

USB 3.0

Xilinx Zynq Ultrascale+ devices feature two built-in USB 3.0 controllers and PHYs, configurable as host or
device. The PHY interface used by the USB 3.0 controller is PIPE3, supporting a 5 Gbit/sec data rate in host
or device modes. The interface of each USB 3.0 controller uses one of the PS GTR lanes.
A 100 MHz differential clock is available on the module and connected to PS_MGTREFCLK2 pins, to be used
as a reference clock for the USB 3.0 interface. It is also possible to provide another reference clock from the
base board to the MGTPS_REFCLK* pins.
D-0000-432-001
Register Value [binary]
0111
0111
01111
0111
0111
11110
Manufacturer
Microchip
33 / 52
Delay Value
0 ps
0 ps
0 ps
0 ps
0 ps
900 ps
Type
USB 2.0 PHY
Version 04, 25.07.2019