Reset; Module Clock Resources; Reset Resources - Enclustra Mars XU3 User Manual

A 24 MHz clock and a 25 MHz clock are used for the USB PHY and Ethernet PHY respectively. The crystal
pads for the MPSoC RTC are connected to a 32.768 kHz oscillator on the Mars XU3 SoC module.
Table 17 describes the clock connections to the MPSoC device.
Signal Name Frequency
CLK33 33.33 MHz
CLK27_GTR_P
27 MHz
CLK27_GTR_N
CLK100_GTR_P
100 MHz
CLK100_GTR_N
PS_PADI
32.768 kHz
PS_PADO
Table 17: Module Clock Resources
2.13

Reset

The power-on reset signal (POR) and the PS system reset signal (SRST) of the MPSoC device are available
on the module connector.
Pulling PS_POR# low resets the MPSoC device, the Ethernet and the USB PHYs, and the QSPI and eMMC
flash devices. Please refer to the Enclustra Module Pin Connection Guidelines [10] for general rules regarding
the connection of reset pins.
Pulling PS_SRST# low resets the MPSoC device and enables the connection between QSPI flash and module
connector, allowing the flash to be programmed from an external SPI master.
For details on the functions of the PS_POR_B and PS_SRST_B signals refer to the Zynq UltraScale+ MPSoC
Technical Reference Manual [19].
Table 18 presents the available reset signals. Both signals, PS_POR# and PS_SRST#, have on-board 10 k
pull-up resistors to VCC_CFG_MIO. For on-board devices using 1.8 V signaling, a PS_POR# low voltage variant
is generated (PS_POR#_LV).
Signal Name
PS_POR#
PS_SRST#
Table 18: Reset Resources
Please note that PS_POR# is automatically asserted if PWR_GOOD is low.
D-0000-432-001
Package Pin
H14
E19
E20
G19
G20
H17
J17
Connector Pin Package Pin
196 K12
192 K13
MPSoC Pin Type
PS_REF_CLK
PS_MGTREFCLK3P_505
PS_MGTREFCLK3N_505
PS_MGTREFCLK2P_505
PS_MGTREFCLK2N_505
PS_PADI (crystal pad input for MPSoC built-in RTC)
PS_PADO (crystal pad output for MPSoC built-in RTC)
FPGA Pin Type
PS_POR_B
PS_SRST_B
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Description
Power-on reset
System reset
Version 04, 25.07.2019