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Mercury+ XU6 SoC Module User Manual Purpose The purpose of this document is to present the characteristics of Mercury+ XU6 SoC module to the user, and to provide the user with a comprehensive guide to understanding and using the Mercury+ XU6 SoC module.
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Unauthorized duplication of this document, in whole or in part, by any means is prohibited without the prior written permission of Enclustra GmbH, Switzerland. Although Enclustra GmbH believes that the information included in this publication is correct as of the date of publication, Enclustra GmbH reserves the right to make changes at any time without notice.
The Enclustra Build Environment [14] is available for the Mercury+ XU6 SoC module. This build system allows the user to quickly set up and run Linux on any Enclustra SoC module. It allows the user to choose the desired target and download all the required binaries, such as bitstream and FSBL (First Stage Boot Loader).
Warning! It is possible to mount the Mercury+ XU6 SoC module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU6 SoC module.
Enclustra Build Environment The Enclustra Build Environment (EBE) [14] enables the user to quickly set up and run Linux on any Enclustra SoC module or system board. It allows the user to choose the desired target, and download all the required binaries, such as bitstream and FSBL.
The Enclustra Build Environment features a graphical user interface (GUI) and a command line interface (CLI) that facilitates the automatic build flow. The Enclustra Build Environment How-To Guide [15] describes in more detail how to use the EBE to customize the provided software for the user application. The document provides information on the configuration options for U-boot, Linux kernel and Buildroot, debugging possibilities for Linux applications, customization of device trees and integration of existing or new kernel drivers.
Please note that the available features depend on the equipped Mercury module type. Xilinx Tool Support The MPSoC devices equipped on the Mercury+ XU6 SoC module are supported by the Vivado HL WebPACK Edition software, which is available free of charge. Please contact Xilinx for further information.
Figure 1: Hardware Block Diagram The main component of the Mercury+ XU6 SoC module is the Xilinx Zynq Ultrascale+ MPSoC device. Most of its I/O pins are connected to the Mercury+ module connector, making up to 254 regular user I/Os avail- able to the user.
Mercury module connectors to supply circuits on the base board. Six LEDs are connected to the MPSoC pins for status signaling. Module Configuration and Product Models Table 1 describes the available standard module configurations. Custom configurations are available; please contact Enclustra for further information. Product Model MPSoC DDR4 (PS)
The correspondence between EN-number and part name is shown in Table 2. The part name represents the product model, followed by the revision; the R suffix and number represent the revision number. The revision changes and product known issues are described in the Mercury+ XU6 SoC Module Known Issues and Changes document [6].
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EN-Number Part Name EN102956 ME-XU6-2CG-1E-D10H-R1.0 EN102958 ME-XU6-2EG-1I-D13E-R1.0 EN102955 ME-XU6-3EG-2I-D11-R1.0 EN102957 ME-XU6-4CG-1E-D12-R1.0 EN102959 ME-XU6-4EV-1I-D12-R1.0 EN102954 ME-XU6-5EV-2I-D12E-R1.0 Table 2: EN-Numbers and Part Names D-0000-464-001 14 / 58 Version 02, 21.07.2021...
Top and Bottom Views 2.4.1 Top View Figure 4: Module Top View 2.4.2 Bottom View Figure 5: Module Bottom View Please note that depending on the hardware revision and configuration, the module may look slightly dif- ferent than shown in this document. D-0000-464-001 15 / 58 Version 02, 21.07.2021...
Figure 8: Module Footprint - Top View Warning! It is possible to mount the Mercury+ XU6 SoC module the wrong way round on the base board - always check that the mounting holes on the base board are aligned with the mounting holes of the Mercury+ XU6 SoC module.
Symbol Value Size 54 mm Component height top 3.32 mm Component height bottom 1.35 mm Weight 28 g Table 3: Mechanical Data Module Connector Three Hirose FX10 168-pin 0.5 mm pitch headers with a total of 504 pins have to be integrated on the base board.
User I/O 2.9.1 Pinout Information on the Mercury+ XU6 SoC module pinout can be found in the Enclustra Mercury Master Pinout [11], and in the additional document Enclustra Module Pin Connection Guidelines [10]. Warning! Please note that the pin types on the schematics symbol of the module connector and in the Master Pinout document are for reference only.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible limitations. Signal Name Sign. Pairs Differential Single- I/O Bank ended IO_B64_<...> In/Out In/Out 64 (HP) 4 signals are routed via level shifters (Refer to Section 2.9.2 for details) IO_B65_<...>...
MIO30/42 does not apply in this case). I/O Pins with Level Shifter There are four signals on the Mercury+ XU6 SoC module that are routed from the FPGA banks to the module connector via level shifters - these are presented in Table 7.
The information regarding the length of the signal lines from the MPSoC device to the module connector is available in Mercury+ XU6 SoC Module IO Net Length Excel Sheet [3]. This enables the user to match the total length of the differential pairs on the base board if required by the application.
Details on connectivity in I/O banks having generic names (for example O or N) are presented in Section 2.9.4. For compatibility with other Enclustra Mercury modules, it is recommended to use a single I/O voltage per module connector.
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Use only VCC_IO voltages compliant with the equipped MPSoC device; any other voltages may dam- age the equipped MPSoC device, as well as other devices on the Mercury+ XU6 SoC module. Do not leave a VCC_IO pin floating, as this may damage the equipped MPSoC device, as well as other devices on the Mercury+ XU6 SoC module.
GPIOs; the suggested functions below are for reference only - always verify your MIO pinout with the Xilinx device handbook. Table 10 gives an overview over the MIO pin connections on the Mercury+ XU6 SoC module. Only the pins marked with “user functionality” are available on the module connector.
ZU4/ZU5 MPSoC devices. GTH Transceivers On modules equipped with ZU4/ZU5 there are 4 GTH MGTs available on the Mercury+ XU6 SoC module - Table 12 describes the connections. The naming convention for the GTH MGT I/Os is: MGT_B<BANK>_<FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
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MGTs at high performance rates. Warning! No AC coupling capacitors are placed on the Mercury+ XU6 SoC module on the MGT lines - make sure capacitors are mounted, if required, on the base board (close to the module pins), to prevent MGT lines from being damaged.
Power Generation Overview The Mercury+ XU6 SoC module uses a 5 - 15 V DC power input for generating the on-board supply voltages (0.72/0.85/0.9 V, 0.85/0.9 V, 0.9 V, 1.2 V, 1.8 V, 2.5 V, 3.3 V and 5.0 V). Some of these voltages (1.8 V, 2.5 V, 3.3 V) are accessible on the module connector.
In this case, VCC_IO needs to be switched off in the manner indicated in Figure 10. 2.11.3 Voltage Supply Inputs Table 15 describes the power supply inputs on the Mercury+ XU6 SoC module. The VCC voltages used as supplies for the I/O banks are described in Section 2.9.5. Pin Name Module Connector Pins...
For Mercury modules an Enclustra heat sink kit is available for purchase along with the product. It repre- sents an optimal solution to cool the Mercury+ XU6 SoC module - the heat sink body is low profile and usually covers the whole module surface. The kit comes with a gap pad for the MPSoC device, a fan and required mounting material to attach the heat sink to the module PCB and baseboard PCB.
TG-A6200-25-25-1 Table 17: Heat Sink Type An Enclustra heatsink for the Mercury+ XU6 SoC module covering the entire module surface is currently un- der development. Until this part is available, the ACC-HS3-Set heatsink kit may be used as an intermediate solution for prototyping purposes.
2.12 Clock Generation A 33.33 MHz oscillator is used for the Mercury+ XU6 SoC module clock generation; the 33.33 MHz clock is fed to the PS. A 100 MHz LVDS oscillator and a 27 MHz CMOS oscillator provide reference clock inputs to the PS GTR bank 505.
2.14 LEDs There are four active-low user LEDs on the Mercury+ XU6 SoC module - all of them are connected to both PS and PL. It is recommended to drive the PL pin to a high impedance state before driving the PS pin and vice versa.
Please check the user manual regularly for updates. Any parts with different speed bins or temperature ranges that fulfill the requirements for the module variant may be used. 2.15.2 Signal Description Please refer to the Mercury+ XU6 SoC Module FPGA Pinout Excel Sheet [4] for detailed information on the DDR4 SDRAM connections. 2.15.3 Termination Warning! No external termination is implemented for the data signals on the Mercury+ XU6 SoC module.
Table 25 describes the memory availability and configuration on the Mercury+ XU6 SoC module. As there is one QSPI flash chip equipped on the Mercury+ XU6 SoC module, type “single” must be selected when programming the flash from Vivado tools.
Table 25: QSPI Flash Type Warning! Other flash memory devices may be equipped in future revisions of the Mercury+ XU6 SoC module. Please check the user manual regularly for updates. Any parts with different speeds and temperature ranges that fulfill the requirements for the module variant may be used.
2.19 Gigabit Ethernet (PS) Two 10/100/1000 Mbit Ethernet PHYs are available on the Mercury+ XU6 SoC module, one connected to the PS via RGMII interface, and one connected to PL via RGMII. 2.19.1 Ethernet PHY Type Table 27 describes the equipped Ethernet PHY (PS) device type on the Mercury+ XU6 SoC module.
The interrupt output of the Ethernet PHY is connected to the I2C interrupt line, available on MIO12 pin. 2.19.3 External Connectivity The Ethernet signal lines can be connected directly to the magnetics. Please refer to the Enclustra Module Pin Connection Guidelines [10] for details regarding the connection of Ethernet signals. 2.19.4 MDIO Address The MDIO address assigned to the ETH PHY is 3, and the PHY can be configured via MIO pins 76-77.
USB 2.0 Two USB 2.0 PHYs are available on the Mercury+ XU6 SoC module, both connected to the PS to I/O bank 502. USB PHY 0 can be configured as host or device, while USB PHY 1 can be used only as host.
USB 2.0 signals from the PHY, all routed to a USB 3.0 connector on the base board. Figure 11: USB 3.0 Implementation Example Warning! The USB 3.0 interface on the Mercury+ XU6 SoC module uses the GTR lines (MGTPS signals on module connector B), and not the USB_SSRX_P/N and USB_SSTX_P/N connections on module connector A. 2.22...
(PMU) - more information on the PMU is available in the Zynq UltraScale+ MPSoC Technical Reference Manual [18]. The RTC crystal pad input and crystal pad output are connected on the Mercury+ XU6 SoC module to a 32.768 kHz oscillator.
3 Device Configuration Configuration Signals The PS of the MPSoC needs to be configured before the FPGA logic can be used. Xilinx Zynq devices need special boot images to boot from QSPI flash, eMMC flash or SD card. For more information, please refer to the Zynq UltraScale+ MPSoC Technical Reference Manual [18].
All configuration signals except for BOOT_MODE must be high impedance as soon as the device is released from reset. Violating this rule may damage the equipped MPSoC device, as well as other devices on the Mercury+ XU6 SoC module. Pull-Up During Configuration The Pull-Up During Configuration signal (PUDC) is pulled to GND on the module;...
Certain Xilinx tool versions support QSPI flash programming via JTAG only when JTAG boot mode is used (unavailable on the Mercury+ XU6 SoC module). Alternatively, the QSPI flash can be programmed in u-boot or Linux by the SPI controller in the PS or from an SPI external master.
The VREF pin of the programmer must be connected to VCC_CFG_MIO. It is recommended to add 22 series termination resistors between the module and the JTAG header, close to the source. Please refer to the Enclustra Module Pin Connection Guidelines for details on JTAG interface. 3.5.3 JTAG Boot Mode...
In the SD card boot mode the PS boots from the SD card located on the base board. There are two SD card boot modes available on the Mercury+ XU6 SoC module. Please note that the SD boot mode with level shifter is currently not supported.
3.12 Enclustra Module Configuration Tool In combination with an Enclustra base board, the QSPI flash can be programmed using Enclustra Module Configuration Tool (MCT) [16]. For this method, a non-QSPI boot mode must be used during QSPI flash programming. The entire procedure is described in the reference design documentation.
4 I2C Communication Overview The I2C bus on the Mercury+ XU6 SoC module is connected to the MPSoC device and to the EEPROM, and is available on the module and debug connectors. This allows external devices to read the module type and to connect more devices to the I2C bus.
An example demonstrating how to read the module information from the EEPROM memory is included in the Mercury+ XU6 SoC module reference design. Warning! The secure EEPROM is for Enclustra use only. Any attempt to write data to the secure EEPROM causes the warranty to be rendered void. 4.4.1...
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Module Configuration Addr. Bits Comment Min. Value Max. Value Comment MPSoC type See MPSoC type table (Table 41) 0x08 MPSoC device speed grade Temperature range See temperature range table (Table 42) Power grade 0 (Normal) 1 (Low power) Gigabit Ethernet port count 0x09 Reserved DDR4 PS bandwidth...
Value MPSoC Device Type XCZU2CG XCZU2EG XCZU3EG XCZU4CG XCZU4EV XCZU5EV Table 41: MPSoC Device Types Table 42 shows the available temperature ranges. Value Module Temperature Range Commercial Extended Industrial Table 42: Module Temperature Range Ethernet MAC Address The Ethernet MAC address is stored using big-endian byte order (MSB on the lowest address). Each module is assigned two sequential MAC addresses;...
5 Operating Conditions Absolute Maximum Ratings Table 43 indicates the absolute maximum ratings for Mercury+ XU6 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [20].
Recommended Operating Conditions Table 44 indicates the recommended operating conditions for Mercury+ XU6 SoC module. The values given are for reference only; for details please refer to the Zynq UltraScale+ MPSoC, DC and AC Switching Characteristics Datasheet [20]. Symbol Description...
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6 Ordering and Support Ordering Please use the Enclustra online request/order form for ordering or requesting information: http://www.enclustra.com/en/order/ Support Please follow the instructions on the Enclustra online support site: http://www.enclustra.com/en/support/ D-0000-464-001 55 / 58 Version 02, 21.07.2021...
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List of Figures Hardware Block Diagram ........Product Model Fields .
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