Power-On Reset Delay Override; Power-On Reset Delay Override (Porsel) - Enclustra Mars XU3 User Manual

Figure 12: Pull-Up During Configuration (PUDC) Resistors - Assembly Drawing Bottom View (upper middle part)
For details on the PUDC signal please refer to the Zynq UltraScale+ MPSoC Technical Reference Manual
[19].
3.3

Power-on Reset Delay Override

The power-on reset delay override MPSoC signal (POR_OVERRIDE) is pulled to GND on the module, setting
the PL power-on delay time to the default standard time.
If the application requires faster PL power-on delay time, this can be achieved by removing R206 component
and by mounting R205.
Figure 13 illustrates the configuration of the I/O signals during power-up. Figure 14 indicates the location of
the pull-up/pull-down resistors on the module PCB - upper middle part on the bottom view drawing.
Figure 13: Power-on Reset Delay Override (PORSEL)
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