Height
Type
4.0 mm
TE 292406-4
5.2 mm
TE 1565917-4
6.5 mm
TE 5-1746530-4
8.0 mm
TE 1827341-4
Table 4: Module Connector Types
2.9
User I/O
2.9.1
Pinout
Information on the Mars XU3 SoC module pinout can be found in the Enclustra Mars Master Pinout [11], and
in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mars XU3 SoC module it may be possible that the
connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B65_L6_AD6_P5_P is located on pin P5 of I/O bank 65, pair 6, it is a System Monitor differ-
ential auxiliary analog input capable pin and it has positive polarity, when used in a differential pair.
The global clock capable pins are marked with "GC" (HP I/O banks) or with "HDGC" (HD I/O banks) in the
signal name. For details on their function and usage, please refer to the Xilinx documentation.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Signal Name
Signals
IO_B65_<...>
48
IO_B66_<...>
4
IO_B26_<...>
24
Total
76
Table 5: User I/Os
The multi-gigabit transceiver (MGT) are described in section 2.10.
1
HD = high density pins, HP = high performance pins; Refer to the Zynq UltraScale+ MPSoC Overview [23] for details.
D-0000-432-001
Description
DDR2-SODIMM, 1.8 V
DDR2-SODIMM, 1.8 V
DDR2-SODIMM, 1.8 V
DDR2-SODIMM, 1.8 V
Pairs
Differential
24
In/Out
2
In/Out
12
In/Out (no LVDS/LVPECL outputs sup-
ported; internal differential termina-
tion not supported)
Refer to Section 2.9.3 for details.
38
-
16 / 52
Max component height under the module
0 mm
1 mm
2 mm
4 mm
Single-ended
In/Out
In/Out
In/Out
-
I/O Bank
1
65 (HP)
1
66 (HP)
1
26 (HD)
-
Version 04, 25.07.2019
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