User I/O; Pinout; Module Connector Types; User I/Os - Enclustra Mars AX3 User Manual

The pinout of the module connector is found in the Mars Master Pinout Excel Sheet [11]. The connector to
be mounted on the base board is available in different heights. Some examples are presented in Table 4.
Please refer to the connector datasheet for more information.
Height Type
4.0 mm TE 292406-4
5.2 mm TE 1565917-4
6.5 mm TE 5-1746530-4
8.0 mm TE 1827341-4
Table 4: Module Connector Types
2.9

User I/O

2.9.1

Pinout

Information on the Mars AX3 FPGA module pinout can be found in the Enclustra Mars Master Pinout [11],
and in the additional document Enclustra Module Pin Connection Guidelines [10].
Warning!
Please note that the pin types on the schematics symbol of the module connector and in the Master
Pinout document are for reference only. On the Mars AX3 FPGA module it may be possible that
the connected pins do not have the targeted functions (such as primary clocks, differential pins, MGT
signals, etc).
The naming convention for the user I/Os is:
IO_B<BANK>_L<PAIR><_SPECIAL_FUNCTION>_<PACKAGE_PIN>_<POLARITY>.
For example, IO_B35_L1_AD4_C6_P is located on pin C6 of I/O bank 35, pair 1, it is an XADC auxiliary analog
input capable pin and it has positive polarity, when used in a differential pair.
The multi-region clock capable pins are marked with "MRCC", while the single region clock capable pins are
marked with "SRCC" in the signal name. For details on their function and usage, please refer to the Xilinx
documentation.
Table 5 includes information related to the total number of I/Os available in each I/O bank and possible
limitations.
Signal Name Signals
IO_B14_<...> 12
IO_B34_<...> 48
IO_B35_<...> 48
Total 108
Table 5: User I/Os
Please note that for the 7 Series FPGAs there are restrictions on the VCCO voltage when using LVDS I/Os;
refer to Xilinx AR# 43989 for details.
D-0000-426-004
Description
DDR2-SODIMM, 1.8 V
DDR2-SODIMM, 1.8 V
DDR2-SODIMM, 1.8 V
DDR2-SODIMM, 1.8 V
Pairs Differential
6 In/Out
24 In/Out
24 In/Out
54 -
15 / 47
Max component height under the module
1 mm
2 mm
3 mm
5 mm
Single-ended
In/Out
In/Out
In/Out
-
I/O Bank
14
34
35
-
Version 06, 16.02.2021