Module Description; Block Diagram; Module Configuration And Product Codes; Hardware Block Diagram - Enclustra Mars AX3 User Manual

2 Module Description

2.1

Block Diagram

Figure 1: Hardware Block Diagram
The main component of the Mars AX3 FPGA module is the Xilinx Artix-7 FPGA device. Most of its I/O pins are
connected to the Mars module connector, making 108 user I/Os available to the user. With some hardware
changes, four additional FPGA pins can be routed to the module connector, in case the application requires
112 user I/Os and a custom base board is used.
The FPGA device can be configured with a bitstream residing in the on-board QSPI flash, via an external
microcontroller or another SPI master device or via the JTAG interface connected to Mars module connector.
The available standard configurations include 256 MB DDR3 SDRAM and 64 MB quad SPI flash.
Further, the module is equipped with a Gigabit Ethernet PHY, making it ideal for communication applications.
On-board clock generation is based on a 50 MHz crystal oscillator.
The module can be operated using a single input supply of 3.3 V DC. All other necessary supply voltages are
generated on-board. Some of these voltages are available on the Mars module connector to supply circuits
on the base board.
A real-time clock may be optionally equipped on the module and connected to the global I2C bus.
Four LEDs are connected to the FPGA pins for status signaling.
2.2

Module Configuration and Product Codes

Table 1 describes the available standard module configurations. Custom configurations are available; please
contact Enclustra for further information.
D-0000-426-004 9 / 47 Version 06, 16.02.2021