Toshiba TLCS-900/L1 Series Manual page 53

(6) Attention point
The instruction execution unit and the bus interface unit of this CPU operate
independently. Therefore, immediately before an interrupt is generated, if the CPU
fetches an instruction that clears the corresponding interrupt request flag, the CPU
may execute the instruction that clears the interrupt request flag (Note) between
accepting and reading the interrupt vector. In this case, the CPU reads the default
vector 0008H and reads the interrupt vector address FFFF08H.
To avoid the avobe plogram, place instructions that clear interrupt request flags
after a DI instruction. And in the case of setting an interrupt enable again by EI
instruction after the execution of clearing instruction, execute EI instruction after
clearing and more than 1-instructions (e.g., "NOP" × 1 times).
In the case of changing the value of the interrupt mask register <IFF2:0> by
execution of POP SR instruction, disable an interrupt by DI instruction before
execution of POP SR instruction.
In addition, take care as the following 2 circuits are exceptional and demand special
attention.
INT0 Level Mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level
mode the interrupt request flip-flop for INT0 does not function. The
peripheral interrupt request passes through the S input of the flip-flop
and becomes the Q output. If the interrupt input mode is changed
from edge mode to level mode, the interrupt request flag is cleared
automatically.
If the CPU enters the interrupt response sequence as a result of
INT0 going from 0 to 1, INT0 must then be held at 1 until the
interrupt response sequence has been completed. If INT0 is set to
level mode so as to release a halt state, INT0 must be held at 1 from
the time INT0 changes from 0 to 1 until the halt state is released.
(Hence, it is necessary to ensure that input noise is not interpreted
as a 0, causing INT0 to revert to 0 before the halt state has been
released.)
When the mode changes from level mode to edge mode, interrupt
request flags which were set in level mode will not be cleared.
Interrupt request flags must be cleared using the following
sequence.
INTRX The interrupt request flip-flop can only be cleared by a reset or by
reading the serial channel receive buffer. It cannot be cleared by
writing INTCLR register.
Note: The following instructions or pin input state changes are equivalent to instructions that
clear the interrupt request flag.
INT0: Instructions which switch to level mode after an interrupt request has been
generated in edge mode.
The pin input change from high to low after interrupt request has been
generated in level mode. (H → L)
INTRX: Instruction which read the receive buffer
DI
LD (IIMC), 00H; Switches interrupt input mode from level
mode to edge mode.
LD (INTCLR), 0AH; Clears interrupt request flag.
NOP ; Wait EI instruction
EI
91C824-51
TMP91C824
2008-02-20