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3.3.3
System Clock Controller
The system clock controller generates the system clock signal (f
and internal I/O. It contains two oscillation circuits and a clock gear circuit for high-
frequency (fc) operation. The register SYSCR1<SYSCK> changes the system clock to
either fc or fs, SYSCR0<XEN> and SYSCR0<XTEN> control enabling and disabling of
each oscillator, and SYSCR1<GEAR0:2> sets the high-frequency clock gear to either 1, 2,
4, 8 or 16 (fc, fc/2, fc/4, fc/8 or fc/16). These functions can reduce the power consumption of
the equipment in which the device is installed.
The combination of settings <XEN> = 1, <XTEN> = 0, <SYSCK> = 0 and <GEAR0:2> =
100 will cause the system clock (f
For example, f
and X2 pins.
(1) Switching from NORMAL mode to SLOW mode
When the resonator is connected to the X1 and X2 pins, or to the XT1 and XT2 pins,
the warm-up timer can be used to change the operation frequency after stable
oscillation has been attained.
The warm-up time can be selected using SYSCR2<WUPTM0:1>.
This warm-up timer can be programmed to start and stop as shown in the following
examples 1 and 2.
Table 3.3.1 shows the warm-up time.
Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-
up timer is not needed.
Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some
variation in warm-up time.
Warm-up Time
SYSCR2
<WUPTM1:0>
8
01 (2
/frequency)
14
10 (2
/frequency)
16
11 (2
/frequency)
) to be set to fc/32 (fc/16 × 1/2) after a reset.
SYS
is set to 1.03 MHz when the 33-MHz oscillator is connected to the X1
SYS
Table 3.3.1 Warm-up Times
Change to
NORMAL Mode
8 (µs)
0.496 (ms)
1.986 (ms)
91C824-18
) for the CPU core
SYS
Change to
SLOW Mode
at f
OSCH
7.8 (ms)
500 (ms)
2000 (ms)
TMP91C824
= 33 MHz,
fs = 32.768 kHz
2008-02-20
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