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3.8.2
Control Registers
Setup bank value and bank use in bank setting register of each local area of LOCAL
register in common area. Moreover, in that case, a combination pin is set up and mapping
is simultaneously setup by the CS/WAIT controller. When CPU outputs logical address of
the local area, MMU outputs physical address to the outside address bus pin according to
value of bank setting register. Access of external memory becomes possible therefore.
7
LOCAL0
Bit symbol
L0E
(0350H)
Read/Write
R/W
After reset
0
Function
BANK for
LOCAL0
0: Disable
1: Enable
7
LOCAL1
Bit symbol
L1E
(0351H)
Read/Write
R/W
After reset
0
Function
BANK for
LOCAL1
0: Disable
1: Enable
7
LOCAL2
Bit symbol
L2E
(0352H)
Read/Write
R/W
After reset
0
Function
BANK for
LOCAL2
0: Disable
1: Enable
7
LOCAL3
Bit symbol
L3E
(0353H)
Read/Write
R/W
After reset
0
Function
BANK
LOCAL3
0: Disable
1: Enable
Note: In case of this TMP91C824, because most upper address bit of physical address is EA25,
most upper address bit of BANK register is meaningless. 4 bits of upper 5-bit address
means 16 BANKs.
LOCAL0 Register
6
5
LOCAL1 Register
6
5
LOCAL2 Register
6
5
LOCAL3 Register
6
5
L3EA26
01000 to 01011:
for
00000 to 00011:
00100 to 00111:
91C824-115
4
3
2
L0EA22
0
Setting BANK number for LOCAL0
"000" setting is prohibited because
it pretend COMMON 0 area
4
3
2
L1EA23
0
Setting BANK number for LOCAL1
"001" setting is prohibited because
it pretend COMMON 0 area
4
3
2
L2EA23
0
Setting BANK number for LOCAL2
"111" setting is prohibited because
it pretend COMMON 0 area
4
3
2
L3EA25
L3EA24
R/W
R/W
R/W
0
0
0
01100 to 01111:
CS2D
CS2B
CS2C
10000 to 11111: Set prohibition
TMP91C824
1
0
L0EA21
L0EA20
R/W
0
0
1
0
L1EA22
L1EA21
R/W
0
0
1
0
L2EA22
L2EA21
R/W
0
0
1
0
L3EA23
L3EA22
R/W
R/W
0
0
CS2E
2008-02-20
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