Toshiba TLCS-900/L1 Series Manual page 46

(4) Detailed description of the transfer mode register
8 bits
DMAM0 to
0 0 0
DMAM3
Number of
Transfer Bytes
000 000 00 Byte transfer
(Fixed)
01 Word transfer
10 4-byte transfer
001 00 Byte transfer
01 Word transfer
10 4-byte transfer
010 00 Byte transfer
01 Word transfer
10 4-byte transfer
011 00 Byte transfer
01 Word transfer
10 4-byte transfer
100 00 Byte transfer
01 Word transfer
10 4-byte transfer
101 00 Counter mode
................... for counting number of times interrupt is generated
DMASn ← DMASn + 1
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Note 1: "n" is the corresponding micro DMA channels 0 to 3
DMADn+/DMASn+: Post-increment (Increment register value after transfer)
DMADn−/DMASn−: Post-decrement (Decrement register value after transfer)
The I/Os in the table mean fixed address and the memory means increment (INC) or decrement
(DEC) addresses.
Note 2: Execution time is under the condition of:
16-bit bus width (Both translation and destination address area)/0 waits/fc = 33 MHz/selected
high-frequency mode (fc × 1)
Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in
the above table.
Note: When setting a value in this register, write 0 to the upper 3 bits.
Mode
Mode Description
Transfer destination address INC mode
............................................ I/O to memory
(DMADn+) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer destination address DEC mode
............................................ I/O to memory
(DMADn−) ← (DMASn)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer source address INC mode
............................................ Memory to I/O
(DMADn) ← (DMASn+)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Transfer source address DEC mode
............................................ Memory to I/O
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
Fixed address mode
.................................................... I/O to I/O
(DMADn) ← (DMASn−)
DMACn ← DMACn − 1
If DMACn = 0, then INTTCn is generated.
91C824-44
TMP91C824
Minimum
Number of
Execution Time
Execution States
at fc = 33 MHz
8 states 485 ns
12 states 727 ns
8 states 485 ns
12 states 727 ns
8 states 485 ns
12 states 727 ns
8 states 485 ns
12 states 727 ns
8 states 485 ns
12 states 727 ns
5 states 303 ns
2008-02-20