Toshiba TLCS-900/L1 Series Manual page 162

2
3.10.5 Control in I C Bus Mode
(1) Acknowledge mode specification
Set the SBI0CR1<ACK> to 1 for operation in the acknowledge mode. The
TMP91C824 generates an additional clock pulse for an acknowledge signal when
operating in master mode. In the transmitter mode during the clock pulse cycle, the
SDA pin is released in order to receive the acknowledge signal from the receiver. In
the receiver mode during the clock pulse cycle, the SDA pin is set to the low in order
to generate the acknowledge signal.
Clear the <ACK> to 0 for operation in the non-acknowledge mode, The TMP91C824
does not generate a clock pulse for the acknowledge signal when operating in the
master mode.
(2) Number of transfer bits
The SBI0CR1<BC2:0> is used to select a number of bits for next transmitting and
receiving data.
Since the <BC2:0> is cleared to 000 as a start condition, a slave address and
direction bit transmission are executed in 8 bits. Other than these, the <BC2:0>
retains a specified value.
(3) Serial clock
a. Clock source
The SBI0CR1<SCK2:0> is used to select a maximum transfer frequency
outputted on the SCL pin in master mode. Set a communication baud rate that
meets the I
on the equations shown below.
t
LOW
t
HIGH
fscl = 1/(t
Note 1:
Note 2:
C bus specification, such as the shortest pulse width of t
2
t t
HIGH
LOW
SBI0CR1<SCK2:0>
n − 1
= 2
/f
SBI
n − 1
= 2 + 8/f
/f
SBI SBI
+ t
)
Low HIGH
f
SBI
=
n
+ 8
2
f is the clock f .
SBI FPH
It's prohibited to use fc/16 prescaler clock when using SBI block. (I
synchronous.)
Figure 3.10.7 Clock Source
91C824-160
1/fscl
n
000 5
001 6
010 7
011 8
100 9
101 10
110 11
TMP91C824
, based
LOW
2
C bus and clock
2008-02-20