Toshiba TLCS-900/L1 Series Manual page 109

In this mode, a programmable square wave is generated by inverting the timer
output each time the 8-bit up counter (UC0) matches the value in one of the timer
registers TA0REG or TA1REG.
The value set in TA0REG must be smaller than the value set in TA1REG.
Although the up counter for TMRA1 (UC1) is not used in this mode,
TA01RUN<TA1RUN> should be set to 1, so that UC1 is set for counting.
Figure 3.7.14 shows a block diagram representing this mode.
Selector
TA0IN
φT1
φT4
φT16
TA01MOD<TA0CLK1:0>
Selector
Shift trigger
TA0REG-WR
Register buffer
TA01RUN<TA0RDE>
Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode
If the TA0REG double buffer is enabled in this mode, the value of the register
buffer will be shifted into TA0REG each time TA1REG matches UC0.
Use of the double buffer facilitates the handling of low-duty waves (when duty is
varied).
Match with TA0REG
and up counter
Match with TA1REG
TA0REG
(Value to be compared)
Register buffer
Figure 3.7.15 Operation of Register Buffer
TA01RUN<TA0RUN>
8-bit
up counter (UC 0)
Comparator Comparator
TA0REG
TA1REG
Internal data bus
(Up counter = Q
)
1
Q
1
Q
2
91C824-107
TA1OUT
TA1FF
TA1FFCR<TA1FFIE>
Inversion
INTTA0
INTTA1
(Up countner = Q
)
2
Shift to register buffer
Q
2
Q
3
TA0REG (Register buffer)
write
TMP91C824
2008-02-20