Toshiba TLCS-900/L1 Series Manual page 168

3.10.6 Data Transfer in I
(1) Device initialization
Set the SBI0BR1<P4EN>, SBI0CR1<ACK, SCK2:0>, Set SBI0BR1 to 1 and clear
bits 7 to 5 and 3 in the SBI0CR1 to 0.
Set a slave address <SA6:0> and the <ALS> (<ALS> = 0 when an addressing
format) to the I2C0AR.
For specifying the default setting to a slave receiver mode, clear 0 to the <MST,
TRX, BB> and set 1 to the <PIN>, 10 to the <SBIM1:0>.
(2) Start condition and slave address generation
a. Master mode
In the master mode, the start condition and the slave address are generated as
follows.
Check a bus free status (when <BB> = 0).
Set the SBI0CR1<ACK> to 1 (Acknowledge mode) and specify a slave address
and a direction bit to be transmitted to the SBI0DBR.
When SBI0CR2<BB> = 0, the start condition are generated by writing 1111 to
SBI0CR2<MST, TRX, BB, PIN>. Subsequently to the start condition, nine clocks
are output from the SCL pin. While eight clocks are output, the slave address
and the direction bit which are set to the SBI0DBR. At the 9th clock, the SDA
line is released and the acknowledge signal is received from the slave device.
An INTSBI interrupt request occurs at the falling edge of the 9th clock. The
<PIN> is cleared to 0. In the master mode, the SCL pin is pulled down to the low
level while <PIN> is 0. When an interrupt request occurs, the <TRX> is changed
according to the direction bit only when an acknowledge signal is returned from
the slave device.
b. Slave mode
In the slave mode, the start condition and the slave address are received.
After the start condition is received from the master device, while eight clocks
are output from the SCL pin, the slave address and the direction bit which are
output from the master device are received.
When a GENERAL CALL or the same address as the slave address set in
I2C0AR is received, the SDA line is pulled down to the low level at the 9th clock,
and the acknowledge signal is output.
An INTSBI interrupt request occurs on the falling edge of the 9th clock. The
<PIN> is cleared to 0. In slave mode the SCL line is pulled down to the low level
while the <PIN> = 0.
SCL line
SDA line A6
Start condtion
<PIN>
INTSBI
interrupt request
Output of master
Output of slave
Figure 3.10.13 Start Condition Generation and Slave Address Transfer
2
C Bus Mode
1 2 3 4
A5 A4 A3
Slave address + Derection bit
91C824-166
5 6 7 8
A2 A1 A0 R/ W
TMP91C824
9
ACK
Acknowledge
signal from a
slave device
2008-02-20