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3.9.1
Block Diagrams
Figure 3.9.2 is a block diagram representing serial channel 0.
Prescaler
φT0
2
4
8
φT2
Serial clock generation circuit
BR0CR
<BR0CK1:0>
BR0CR
<BR0S3:0>
φT0
φT2
φT8
φT32
f
SYS
SCLK0
Concurrent
with PC2
I/O interface mode
SCLK0
Concurrent
with PC2
Receive
counter
(UART only ÷ 16)
RXDCLK
SC0MOD0
Receive control
<RXE>
Receive buffer 1 (Shift register)
RXD0
Concurrent
with PC1
RB8
Receive buffer 2 (SC0BUF)
Figure 3.9.2 Block Diagram of the Serial Channel 0 (SIO0)
16 32 64
φT8 φT32
TA0TRG
(from TMRA0)
BR0ADD
<BR0K3:0>
BR0CR
<BR0ADDE>
SC0MOD0
<SC1:0>
Baud rate
generator
÷2
SC0CR
<IOC>
SC0MOD0
Serial channel
<WU>
interrupt
control
SC0CR
<PE>
<EVEN>
Parity control
Error flag
SC0CR
<OERR><PERR><FERR>
Internal data bus
91C824-123
UART
mode
SIOCLK
SC0MOD0
<SM1:0>
I/O
interface mode
Transmision
counter
(UART only ÷ 16)
TXDCLK
Transmission
control
SC0MOD0
<CTSE>
Transmission buffer (SC0BUF)
TB8
TMP91C824
INT request
INTRX0
INTTX0
CTS0
Concurrent
with PC2
TXD0
Concurrent
with PC0
2008-02-20
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