Toshiba TLCS-900/L1 Series Manual page 196

3.12.2 Control Registers
The watchdog timer WDT is controlled by two control registers WDMOD and WDCR.
(1) Watchdog timer mode register (WDMOD)
a. Setting the detection time for the watchdog timer in <WDTP1:0>
This 2-bit register is used for setting the watchdog timer interrupt time used
when
WDMOD<WDTP1:0> = 00.
The detection times for WDT are shown in Figure 3.12.4.
b. Watchdog timer enable/disable control register <WDTE>
After reset, WDMOD<WDTE> is initialized to 1, enabling the watchdog timer.
To disable the watchdog timer, it is necessary to set this bit to 0 and to write the
disable code (B1H) to the watchdog timer control register WDCR. This makes it
difficult for the watchdog timer to be disabled by runaway.
However, it is possible to return the watchdog timer from the disabled state to
the enabled state merely by setting <WDTE> to 1.
c. Watchdog timer out reset connection <RESCR>
This register is used to connect the output of the watchdog timer with the
RESET terminal internally. Since WDMOD<RESCR> is initialized to 0 on reset,
a reset by the watchdog timer will not be performed.
(2) Watchdog timer control register (WDCR)
This register is used to disable and clear the binary counter for the watchdog timer.
Disable control the watchdog timer can be disabled by clearing WDMOD<WDTE>
to 0 and then writing the disable code (B1H) to the WDCR register.
WDMOD
WDCR
•
Enable control
Set WDMOD<WDTE> to 1.
• Watchdog timer clear control
To clear the binary counter and cause counting to resume, write the clear code
(4EH) to the WDCR register.
WDCR
Note1: If it is used disable control, set the disable code (B1H) to WDCR after write the clear code (4EH) once.
(Please refer to setting example.)
Note2: If it is changed Watchdog timer setting, change setting after set to disable condition once.
detecting runaway. After
← 0 – – X X – – –
← 1 0 1 1 0 0 0 1
← 0 1 0 0 1 1 1 0
91C824-194
reset, this register
Clear WDMOD<WDTE> to 0.
Write the disable code (B1H).
Write the clear code (4EH).
TMP91C824
is initialized to
2008-02-20