Toshiba TLCS-900/L1 Series Manual page 135

(12) Timing generation
a. In UART mode
Receiving
Mode
Interrupt timing
Framing error timing
Parity error timing
Overrun error timing
Note: In 9-Bit and 8-Bit+Parity mode, interrupts coincide with the ninth bit pulse.Thus,
when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to
be transferred) to allow checking for a framing error.
Transmitting
Mode
Interrupt timing
b. I/O interface
Transmission SCLK output mode
interrupt
SCLK input mode
timing
Receiving SCLK output mode
interrupt
timing
SCLK input mode
8 Bits + Parity
9 Bits (Note)
(Note)
Center of last bit Center of last bit
(Bit8) (Parity bit)
Center of stop bit Center of stop bit
Center of last bit
−
(Parity bit)
Center of last bit Center of last bit
(Bit8) (Parity bit)
8 Bits + Parity
9 Bits
Just before stop Just before stop bit is
bit is transmitted transmitted
Immediately after the last bit. (See Figure 3.9.19.)
Immediately after rise of last SCLK signal rising mode, or
immediately after fall in falling mode. (See Figure 3.9.20.)
Timing used to transfer received to data receive buffer 2 (SC0BUF)
(e.g., immediately after last SCLK). (See Figure 3.9.21.)
Timing used to transfer received data to receive buffer 2 (SC0BUF)
(e.g., immediately after last SCLK). (See Figure 3.9.22.)
91C824-133
TMP91C824
8 Bits, 7 Bits + Parity,
7 Bits
Center of stop bit
Center of stop bit
Center of stop bit
Center of stop bit
8 Bits, 7 Bits + Parity, 7 Bits
Just before stop bit is transmitted
2008-02-20