Toshiba TLCS-900/L1 Series Manual page 259

(2) Points of note
a. AM0 and AM1 pins
This pin is connected to the VCC or the VSS pin. Do not alter the level when the pin is
active.
b. EMU0 and EMU1
Open pins.
c. Reserved address areas
The TMP91C824 does not have any reserved areas.
d. HALT mode (IDLE1)
When IDLE1 mode is used (in which oscillator operation only occurs), set RTCCR
<RTCRUN> to 0 stop the timer for the real-time clock before the HALT instructions is
executed.
e. Warm-up counter
The warm-up counter operates when STOP mode is released, even if the system is using
an external oscillator. As a result a time equivalent to the warm-up time elapses between
input of the release request and output of the system clock.
f. Programmable pull-up resistance
The programmable pull-up resistor can be turned ON/OFF by a program when the ports
are set for use as input ports. When the ports are set for use as output ports, they cannot
be turned on/off by a program.
The data registers (e.g., Px) are used to turn the pull-up/pull-down resistors ON/OFF.
Consequently read-modify-write instructions are prohibited.
g. Bus release function
It is described note point in 3.5 "Port Function" that pin's conditions at bus release
condition.
Please refer that.
h. Watchdog timer
The watchdog timer starts operation immediately after a reset is released. When the
watchdog timer is not to be used, disable it.
When the bus is released, neither internal memory nor internal I/O can be accessed.
However, the internal I/O continues to operate. Hence the watchdog timer continues to
run. Therefore be careful about the bus releasing time and set the detection timer of
watchdog timer.
i. AD converter
The string resistor between the VREFH and VREFL pins can be cut by a program so as
to reduce power consumption. When STOP mode is used, disable the resistor using the
program before the HALT instruction is executed.
j. CPU (Micro DMA)
Only the LDC cr, r and LDC r, cr instructions can be used to access the control registers
in the CPU (e.g., the transfer source address register (DMASn)).
k. Undefined SFR
The value of an undefined bit in an SFR is undefined when read.
l. POP SR instruction
Please execute the POP SR instruction during DI condition.
91C824-257
TMP91C824
2008-02-20