Toshiba TLCS-900/L1 Series Manual page 192

(5) AD conversion time
84 states (5.1 µs at f
channel.
(6) Storing and reading the results of AD conversion
The AD conversion
ADREG37H/L) store the AD conversion results. (ADREG04H/L to ADREG37H/L are
read-only registers.)
In channel fixed repeat conversion mode, the conversion results are stored
successively in registers ADREG04H/L to ADREG37H/L. In other modes, the AN0
and AN4, AN1 and AN5, AN2 and AN6, and AN3 and AN7 conversion results are
stored in ADREG04H/L,
respectively.
Table 3.11.3 shows the correspondence between the analog input channels and the
registers which are used to hold the results of AD conversion.
Table 3.11.3 Correspondence between Analog Input Channels
and AD Conversion Result Registers
Analog Input
Channel (Port 8)
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
<ADRxRF>, bit0 of the AD conversion data lower register, is used as the AD
conversion data storage flag. The storage flag indicates whether the AD conversion
result register has been read or not. When a conversion result is stored in the AD
conversion result register, the flag is set to 1. When either of the AD conversion result
registers (ADREGxH or ADREGxL) is read, the flag is cleared to 0.
Reading the AD conversion result also clears the AD conversion end flag
ADMOD0<EOCF> to 0.
= 33 MHz) are required for the AD conversion for one
FPH
data upper and lower
ADREG15H/L,
AD Conversion Result Register
Channel Fixed Repeat
Conversion Modes
Conversion Mode
Other than at Right
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
91C824-190
TMP91C824
registers (ADREG04H/L
ADREG26H/L and ADREG37H/L
(<ITM0> = 1)
ADREG04H/L
ADREG15H/L
ADREG26H/L
ADREG37H/L
to
2008-02-20