Toshiba TLCS-900/L1 Series Manual page 24

3.3.4 Prescaler Clock Controller
For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1) there is a prescaler which can
divide the clock.
The φT0 clock input to the prescaler is either the clock f
fc/16 divided by 4. The setting of the SYSCR0<PRCK0:1> register determines which clock
signal is input.
3.3.5 Clock Doubler (DFM)
DFM outputs the f
low-frequency oscillator, even though the internal clock is high frequency.
A reset initializes DFM to stop status, setting to DFMCR0 register is needed before use.
Like an oscillator, this circuit requires time to stabilize. This is called the lockup time.
The following example shows how DFM is used.
DFMCR0 EQU
DFMCR1 EQU
LD
LD
LUP: BIT
JR
LD
X: Don't care
ACT1:0
DFM output: f
DFM
Lockup timer
<DLUPFG>
System clock f
SYS
Note: Input frequency limitation and correction for DFM
Recommend to use input frequency (High-speed oscillation) for DFM in the following
condition.
= 4 to 8.25 MHz (Vcc = 2.7 V to 3.6 V): Write 0BH to DFMCR1
f
OSCH
= 2 to 2.5 MHz (Vcc = 2.0 V ± 10%): Write 1BH to DFMCR1
f
OSCH
clock signal, which is four times as fast as f
DFM
00E8H
00E9H
(DFMCR1), 00001011B
(DFMCR0), 01−0XXXXB ;
5, (DFMCR0) ;
NZ, LUP ;
(DFMCR0), 10−0XXXXB ;
01
Counts up by f
OSCH
During lockup
Starts DFM operation.
Starts lockup.
91C824-22
divided by 4 or the clock
FPH
DFM parameter setting
12
Set lockup time to 2 /4 MHz
Enables DFM operation and starts lockup
Detects end of lockup
Changes fc from 4 MHz to 16 MHz
Changes f from 2 MHz to 8 MHz
SYS
10
After lockup
Changes from 4 MHz to 16 MHz.
Ends of lockup
TMP91C824
. It can use the
OSCH
2008-02-20