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At Figure 3.8.3, it shows example of connection TMP91C824 and some memories:
Program ROM: MROM, 16 Mbytes, data ROM: MROM, 64 Mbytes, data RAM: SRAM, 8
Mbytes, 8-bit bus, option ROM: Flash, 16 Mbytes.
In case of 16-bit bus memory connection, it need to shift 1-bit address bus from
TMP91C824 and 8-bit bus case, direct connection address bus from TMP91C824.
In that figure, logical address and physical address are shown. And each memory allot
each chip select signal, RAM:
MROM:
. In case of this example, as data MROM is 64 Mbytes, this MROM connect to
CS3
EA24 and EA25.
Initial condition after reset, because TMP91C824 access from
to program ROM. It can set free setting except program ROM.
;Initial Setting
;CS0
LD
(MSAR0),00H
LD
(MAMR0),FFH ; Logical address size: 2 Mbytes
LD
(B0CS),89H
;CS1
LD
(MSAR1),40H
LD
(MAMR1),FFH ; Logical address size: 4 Mbytes
LD
(B1CS),80H
;CS2
LD
(MSAR2),C0H
LD
(MAMR2),7FH
LD
(B2CS),C3H
;CS3
LD
(MSAR3),80H
LD
(MAMR3),7FH
LD
(B3CS),85H
;CSX
LD
(BEXCS),00H
;Port
LD
(P6FC), 3FH
Figure 3.8.4 BANK Operation S/W Example 1
Secondly, it shows example of initial setting at Figure 3.8.4.
Because
connect to RAM: 8-bit bus, 8 Mbytes, it need to set 8-bit bus. At this
CS0
example, it set 1-wait setting. In the same way
16-bit bus and 0 waits,
By CS/WAIT controller, each chip selection signal's memory size, don't set actual
connect memory size, need to set that logical address size: fitting to each local area. Actual
physical address is set by each area's BANK register setting.
CSX setting of CS/WAIT controller is except above CS0 to CS3's setting. This program
example isn't used CSX setting.
Finally pin condition is set. Port 60 to 65 set to
,
ROM:
CS0
FLASH
; Logical address area: 000000H to 1FFFFFH
; Condition: 8 bits, 1 wait (8 Mbytes, SRAM)
; Logical address area: 400000H to 7FFFFFH
; Condition: 16 bits, 2 waits (16 Mbytes, Flash ROM)
; Logical address area: C00000H to FFFFFFH
; Logical address size: 4 Mbytes
; Condition: 16 bits, 0 waits (16 Mbytes, MROM)
; Logical address area: 800000H to BFFFFFH
; Logical address size: 4 Mbytes
; Condition: 16 bits, 3 waits (64 Mbytes, MROM)
; Other : 16 bits, 2 waits (Don't care)
;
to
, EA24, EA25: Port 6 setting
CS0
CS3
CS1
set 16-bit bus and 3 waits.
CS3
91C824-117
, program MROM:
CS1
area,
CS2
set to 16-bit bus and 2 waits,
,
,
,
, EA24, EA25.
CS0
CS1
CS2
CS3
TMP91C824
, data
CS2
area allot
CS2
set
CS2
2008-02-20
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