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Example: To generate 1/4-duty 50-kHz pulses (at fc = 33 MHz)
20 µs
* Clock state
Calculate the value which should be set in the timer register.
To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 µs
φT1 = (2
/fc)s (at 33 MHz);
3
20 µs ÷ (2
/fc)s ≈ 83
3
Therefore set TA1REG = 83 = 53H
The duty is to be set to 1/4: t × 1/4 = 20 µs × 1/4 = 5 µs
5 µs ÷ (2
/fc)s ≈ 10
3
Therefore, set TA0REG = 21 =15H.
7
6
5
4
← –
TA01RUN
X
X
X
← 1
TA01MOD
0
X
X
← 0
TA0REG
0
0
1
← 0
TA1REG
1
0
1
← X
TA1FFCR
X
X
X
← X
PBCR
–
–
–
← X
PBFC
–
–
–
← 1
TA01RUN
X
X
X
X: Don't care, −: No change
System clock:
Clock gear:
Prescaler clock: f
3
2
1
0
–
0
0
0
Stop TMRA0 and TMRA01 and clear it to 0.
Set the 8-bit PPG mode, and select φT1 as input clock.
X
X
0
1
0
1
0
1
Write 15H
0
0
1
1
Write 53H
0
1
1
X
Set TA1FF, enabling both inversion and the double buffer.
Writing 10 provides negative logic pulse.
–
–
1
–
Set PB1 as the TA1OUT pin.
–
–
1
X
–
1
1
1
Start TMRA0 and TMRA01 counting.
91C824-108
TMP91C824
High frequency (fc)
1 (fc)
FPH
2008-02-20
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