Toshiba TLCS-900/L1 Series Manual page 33

Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation
Status of Received Interrupt
HALT Mode
NMI
INTWDT
INT0 to INT3 (Note 1)
INTALM0 to INTALM4
INTTA0 to INTTA3
INTRX0 to INTRX1, TX0 to TX1
INTAD
INTRTC
INTSBI
RESET
♦:
After clearing the HALT mode, CPU starts interrupt processing.
○
: After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT
instruction.
×:
It can not be used to release the HALT mode.
−:
The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority
level. There is not this combination type.
*1: Releasing the HALT mode is executed after passing the warm-up time.
Note: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled
status, hold level "H" until starting interrupt processing. If level "L" is set before holding level "L",
interrupt processing is correctly started.
(Example: Clearing IDLE1 mode)
An INT0 interrupt clears the halt state when the device is in IDLE1 mode.
Address
8200H LD
8203H LD
8206H LD
8209H EI
820BH LD
820EH HALT
INT0
820FH LD
Interrupt Enabled
(Interrupt level) ≥ (Interrupt mask)
IDLE2 IDLE1 STOP
♦
♦
♦
♦
♦
♦
♦
♦
♦
(PBFC), 08H ; Sets PB3 to INT0.
(IIMC), 00H ; Selects INT0 interrupt rising edge.
(INTE0AD), 06H ; Sets INT0 interrupt level to 6.
5 ; Sets interrupt level to 5 for CPU.
(SYSCR2), 28H ; Sets HALT mode to IDLE1 mode.
; Halts CPU.
XX, XX
91C824-31
Interrupt Disabled
(Interrupt level) < (Interrupt mask)
IDLE2
*1
♦ ♦ −
× −
×
*1 ○
♦
♦
○
♦
×
× ×
×
× ×
×
× ×
×
○
♦
×
× ×
×
Reset initializes the LSI
INT0 interrupt routine
RETI
TMP91C824
IDLE1 STOP
− −
− −
*1
○ ○
○
×
×
×
×
×
×
×
○
×
×
×
2008-02-20