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3.14.1
Block Diagram
[Melody generator]
Low-speed
clock
(32.76 kHz)
[Alarm generator]
Internal data bus
MELFH, MELFL register
MELFH
<MELON>
Comparator (CP0)
Stop&clear
12-bit counter (UC0)
15-bit counter (UC1)
4096 Hz
MELALMC
8-bit counter (UC2)
<FC1:0>
Alarm wave form
generator
ALM resistor
Internal data bus
Figure 3.14.1 MLD Block Diagram
91C824-214
Reset
MELOUT
Invert
F/F
Clear
Edge
detector
ALMINT
<IALM4E:0E>
MELOUT
Selector
Invert
ALMOUT
MELALMC
MELALMC
<MELALM>
>
<ALMINV
Reset
TMP91C824
INTALM0 (8192 Hz)
INTALM1 (512 Hz)
INTALM2 (64 Hz)
INTALM3 (2 Hz)
INTALM4 (1 Hz)
INTALMH
(Halt release)
MLDALM pin
2008-02-20
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