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2
3.10.4
I
C Bus Mode Control
The following registers are used to control and monitor the operation status when using
the serial bus interface (SBI) in the I
7
SBI0CR1
Bit symbol
BC2
(0240H)
Read/Write
After reset
0
Prohibit
Function
Number of transferred bits (Note 1) Acknowledge
read-
modify-
write
Note 1: Set the <BC2:0> to 000 before switching to a clock-synchronous 8-bit SIO mode.
Note 2: For the frequency of the SCL line clock, see 3.10.5 (3) Serial clock.
Note 3: Initial data of SCK0 is "0", SWRMON is "1".
2
Note 4: This I
C bus circuit does not support fast mode, it supports standard mode only. Although the I
circuit itself allows the setting of a baud rate over 100kbps, the compliance with the I
guraranteed in that case.
C bus mode.
2
Seirial Bus Interface Conrol Register 1
6
5
4
BC1
BC0
ACK
W
R/W
0
0
0
mode
specification
0: Not
generate
1: Generate
Internal serial clock selection <SCK2:0> at write
Software reset state monitor <SWRMON> at read
Acknowledge mode specification
Number of bits transferred
Figure 3.10.3 Registers for the I
91C824-156
3
2
SCK2
W
0
Internal serial clock selection and
software reset monitor (Note 2)
n = 5
000
-
Note 4
n = 6
001
-
Note 4
n = 7
010
-
Note 4
n = 8
011
-
Note 4
n = 9
100
63.5 kHz
n = 10
101
32.0 kHz
n = 11
110
16.1 kHz
111
(Reserved)
0
During software reset
1
Initial data
0
Not generate clock pulse for acknowledge signal
1
Generate clock pulse for acknowledge signal
<ACK> = 0
<BC2:0>
Number of
Bits
clock pulses
000
8
8
001
1
1
010
2
2
011
3
3
100
4
4
101
5
5
110
6
6
111
7
7
2
C Bus Mode
TMP91C824
1
0
SCK0/
SCK1
SWRMON
R/W
0
0/1 (Note 3)
System clock: fc
Clock gear: fc/1
fc = 33 MHz
(internal SCL output)
fc
fscl =
[Hz]
n
2
+ 8
<ACK> = 1
Number of
Bits
clock pulses
9
8
2
1
3
2
4
3
5
4
6
5
7
6
8
7
2
C bus
2
C specification is not
2008-02-20
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