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•
Bits 5-0: SPC 5-0, respectively (states of the Stimulus Pattern Clocks; each should be set in exactly
one subcycle of any cycle)
Response TG Memory Data (Read/Write)
Each location in this memory corresponds to one subcycle in a timing cycle and gives the states of the six
response pattern clocks for that subcycle. Bits 15-7 are "don't-care" when writing and give 1's when read.
Bits 5-0 give the values last written to them when read.
Address: Base + 26
H
Bit #
15
14
13
Value
X
X
X
Bit Definitions
•
Bits 5-0: RPC 5-0, respectively (states of the Response Pattern Clocks; each should be set in exactly
one subcycle of any cycle)
Prescaler Divide Ratio (Read/Write)
Each subcycle of every timing cycle will have a duration which is (N+ 1)*6.25ns, where N is the 16-bit
unsigned integer in this register. There is a delay of up to 2us before new values take effect. Reading this
location gives the last value written.
Address: Base + 28
H
Bit #
15
14
13
Value
Value = N - 1 Where: N is the desired ratio. N can range from 1 to 65,536.
Stimulus TG Memory Address (Read Only)
Bits 15-10 give 1's when read; Bits 9-0 give the current state of the stimulus timing generator's address
counter. (Readback of the main high-speed address counter.)
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12
11
10
9
8
X
X
X
X
X
12
11
10
9
8
Prescaler Divide Ratio
7
6
5
4
X
X
IN
IN
TICK5
TICK4
TICK3
7
6
5
4
3
3
2
1
0
IN
IN
IN
IN
TICK2
TICK1
TICK0
2
1
0
Register Maps 3-17
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