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Trigger Control (Read/Write)
Bits 15-8 of this register are "don't-care" when writing and give 1's when read. Bits 7-0 configure the
trigger subsystem and give the last values written when read.
Address: Base + 08
H
Bit #
15
14
13
Value
X
X
X
Bit Definitions
•
Bit 7: QUAL OFF* (1 = trigger qualifier is forced to be true regardless of the contents of the truth
table memory, resulting in unqualified triggering)
•
Bit 6: TRIG IMMED (0-to-1 transition causes an immediate trigger, overriding all other sources)
•
Bit 5: TRIG EN (0 = all sources except "Immediate" are disabled)
•
Bits 4-0: TRIG SOURCE SELECT (select the trigger source and slope):
00000 = Pod, rising edge
00001 = Pod, falling edge
00010 = Front-panel TTL, rising edge
00011 = Front-panel TTL, falling edge
00100 = Front-panel ECL, rising edge
00101 = Front-panel ECL, falling edge
00110 = VXIbus Backplane ECLTRG0, rising edge
00111 = VXIbus Backplane ECLTRG1, rising edge
01000 = VXIbus Backplane TTLTRG0, falling edge
01001 = VXIbus Backplane TTLTRG1, falling edge
01111 = VXIbus Backplane TTLTRG7, falling edge
1XXXX = Immediate (module is triggered immediately upon being armed).
Branch Destination (Read/Write)
When Branch Mode is enabled (Bit 6 of Status/Control # 1 is set to 1), then this register supplies the
location to which the jump is made when the sequencer encounters a Marker. All 16 bits are significant,
and reading this location gives the last value written.
Address: Base + 0C
H
Bit #
15
14
13
Value
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12
11
10
9
8
X
X
X
X
X
QUAL OFF*
.
.
12
11
10
9
Branch Destination
7
6
TRIG IMMED
TRIG EN.
8
7
6
5
5
4
3
2
1
TRIG SOURCE SELECT
4
3
2
1
Register Maps 3-9
0
0
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