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Figure 1-2. Timing Module Block Diagram
combinations of the 10 "Q" lines) within a test. An additional expression evaluator is provided for trigger
qualification.
Programmable marker outputs available from SMB connectors on the front panel of the Timing Module
or the VXIbus trigger bus lines, can be used to trigger other VXIbus or GP-IB instruments. Bus "wait
states" can be implemented with the end-if-ready function in conjunction with the ready input.
Emulation of complex bus cycles is made possible with up to 256 timing cycles. The Timing Module also
supplies eight general-purpose control signals for strobes, clocks, etc., to the DUT.
The Agilent E1450 provides 12 pattern clocks (six for stimulus, six for response) to one or more
E1451/E1452 Pattern I/O Modules in the same VXIbus mainframe for synchronizing ports that must
clock together. For large test systems exceeding the capacity of one VXIbus mainframe, a second or
third mainframe may be connected using the Agilent E1482 VXIbus Extender. One E1450 Timing
Module located in the root mainframe can act as a master for two additional E1450 slaves located in the
extended mainframes. Control of a total of 30 Pattern I/O Modules (960 pins) is possible given that the
mainframe can deliver sufficient power. Master/slave assignment is done by connecting a master/slave
cable from a master connector on the master module to the slave connector on each of the slaves.
1-2 Hardware Descriptions
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