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Sequencer Memory Data (Read/Write)
Each location in this memory corresponds to one timing cycle. For that cycle, it defines the location of
the first subcycle in the timing generator memories, and determines whether or not to arm the trigger,
generate a marker, cause a breakpoint or end the sequence. Bits 13, 12, 9 and 8 are "don't-care" when
writing and give 1's when read. All other bits give the last values written when read (assuming no AUTO
INCR). If bit 5 of the Status/Control Register # 1 (06
of the Status/Control Register # 1 (06
Address: Base + 12
H
Bit #
15
14
13
Value
BKPT
TRIG ARM
Bit Definitions
•
Bit 15: BRKPT (1 = a breakpoint will occur before this cycle)
•
Bit 14: TRIG ARM (1 = the trigger will be armed before this cycle)
•
Bit 11: MARKER (1 = a marker pulse will be generated in this cycle)
•
Bit 10: EOS (1 = this cycle is the end of the sequence)
•
Bits 7-0: TIMING CYCLE TAG (the first subcycle of this cycle is located at the timing generator
memory location which has an address equal to four times this value)
High-Speed Memory Address (Read/Write)
This register can be substituted for the normal sequencer output by setting Bit 0 of Status/Control # 1 to
1. It is also used to address the three timing generator memories and the truth table memories when
loading or reading them. When accessing these memories, Bits 1 and 0 of Status/Control # 1 must be set
to 1. Bits 13 and 12 of this register are "don't-care" when writing; when read, all 16 bits give the last values
written to them.
Address: Base + 14
H
Bit #
15
14
Value
BKPT
TRIG ARM
Bit Definitions
•
Bit 15: BRKPT
•
Bit 14: TRIG ARM
•
Bit 11: MARKER
•
Bit 10: EOS
•
Bits 9-0: HIGH-SPEED MEMORY ADDRESS (bits 0 and 1 have no effect when using this regster
as sequence memory substitute)
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) is set, the LSByte cannot be written to.
h
12
11
X
X
TRIG OUT (& BRA)
13
12
11
10
X
X
TRIG OUT
EOS
) is set, the MSByte cannot be written to. If bit 4
h
10
9
8
7
6
EOS
X
X
9
8
7
6
5
High-Speed Memory Address
5
4
3
2
1
Timing Cycle Tag
4
3
2
1
Register Maps 3-11
0
0
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