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Address: Base + 2A
H
Bit #
15
14
13
Value
X
X
X
Timing Generator Delay (Read/Write)
Bits 15-8 of this register are "don't-care" when writing and give 1's when read. Bits 7-4 set the Control
Timing Generator's delay and Bits 3-0 set the Response Timing Generator's delay. Bits 7-0 give the last
values written to them when read.
Address: Base + 2C
H
Bit #
15
14
13
Value
X
X
X
Bit Definitions
•
Bits 7-4: CONTROL TG DELAY
0000 = Minimum
0001 = Minimum + 1.56ns
0010 = Minimum + 3.13ns
.
.
1111 = Minimum + 23.44ns
•
Bits 3-0: RESPONSE TG DELAY
0000 = Minimum
0001 = Minimum + 6.25ns
0010 = Minimum + 12.5ns ...
.
.
1011 = Minimum + 68.75ns
11xx = Illegal
Trigger Output Control
Bits 15-10 of this register are "don't-care" when writing and give 1's when read. Bits 9-0 specify which, if
any, of the backplane trigger busses are to be driven with the marker pulse, and give the last values
written when read.
3-18 Register Maps
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12
11
10
9
8
X
X
X
12
11
10
9
8
X
X
X
X
X
7
6
5
4
3
T.G. Memory Address
7
6
5
4
3
CONTROL TG DELAY
RESPONSE TG DELAY
2
1
0
2
1
0
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