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Command Register (Read/Write)
Bits 15-2 of this register are "don't-care" when writing and give 1's when read. Bits 1-0 specify a command
to the module and give the last values written when read.
Address: Base + 22
H
Bit #
15
14
13
Value
X
X
X
Bit Definitions
•
Bits 1-0: Command:
00 = INIT (resets various state machines and clocks the sequencer once to make control
information from the first step of the sequence available to the timing generators; aborts any
sequence which is in progress)
01 = RUN (takes the timing generators from a properly initialized or Paused state to the Running
condition)
10 = SET PAUSE (sets a flag which causes the timing generators to enter the Paused state at the
end of the current cycle; issuing a RUN command while this flag is set causes one cycle to occur)
11 = CLEAR PAUSE (clears the pause flag; issuing a RUN command while the flag is cleared
causes the sequence to continue)
NOTE: Bits 0 and 1 are cleared (an INIT command is issued) by a hard or soft reset.
Stimulus TG Memory Data (Read/Write)
Each location in this memory corresponds to one subcycle in a timing cycle and gives the states of the six
stimulus pattern clocks and six control bits for that subcycle. Bits 15-12 are "don't-care" when writing and
give 1's when read. Bits 11-0 give the values last written to them when read (assuming address has not
changed and HSMA MODE = 1).
Address: Base + 24
H
Bit #
15
14
13
Value
X
X
X
Bit Definitions
•
Bit 11: TC2* (0 = test COND2 and wait if necessary for it to become true; 1 = ignore COND2)
•
Bit 10: TC1* (0 = test COND1 and wait if necessary for it to become true; 1 = ignore COND1)
•
Bit 9: TC0* (0 = test COND0 and wait if necessary for it to become true; 1 = ignore COND0)
•
Bit 8: TRIG PULSE* (0 = assert the selected backplane ECL trigger bus(es) if the sequencer
specifies a marker in this cycle; should be 0 in the first two subcycles of every cycle and 1 in the
remaining subcycles)
•
Bit 7: NEOCIR --End if ready--(1 = the next subcycle will be the current cycle's last if the Ready
input(s) are true).
•
Bit 6: NEOC (1 = the next subcycle will be the current cycle's last, unconditionally)
3-16 Register Maps
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12
11
10
9
8
X
X
X
X
X
12
11
10
9
8
X
TC2* TC1* TC0*
TRIG
PULSE*
7
6
5
4
3
X
X
X
X
X
7
6
5
4
NEOCIR NEOC
OUT
OUT
TICK5
TICK4
2
1
0
X
COMMAND
BITS
3
2
1
0
OUT
OUT
OUT
OUT
TICK3
TICK2
TICK1
TICK0
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