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Truth Table Memory Data (Read/Write)
Bits 15-8 of this register are "don't-care" when writing and give 1's when read. Bit 7 is "don't-care" when
writing and gives 0 when read. Bits 6-4 are "don't-care" when writing but give the states of Ready and
Trigger inputs when read. Bits 3-0 correspond to the four bits of the truth table memory. Each location of
this memory corresponds to a state of the Q9-Q0 inputs and gives the states of the four CONDitions for
that state of Q9-Q0. When read, these bits give the values last written to that location. This register
cannot be written to unless HSMA MODE (bit 1 in the Status/Control Register # 1) is set.
Address: Base + 16
H
Bit #
15
14
13
12
Value
X
X
X
X
Bit Definitions
•
Bit 6: FP READY (gives the state of the front-panel Ready input)
•
Bit 5: POD READY (gives the state of the pod's Ready input)
•
Bit 4: TRIG STATE (gives the state of the trigger selector's output; this bit is valid even when
triggers are disabled)
•
Bit 3: COND3 (trigger qualifier function)
•
Bit 2: COND2
•
Bit 1: COND1
•
Bit 0: COND0
Control TG Memory Data (Read/Write)
Each location in this memory corresponds to one subcycle in a timing cycle. For that subcycle, this
memory gives the states of the eight control output lines. Bits 15-8 are "don't-care" when writing and give
1's when read. Bits 7-0 correspond to Control Outputs 7-0, respectively, and give the values last written
to that location when read.
Address: Base + 18
H
Bit #
15
14
13
Value
X
X
X
3-12 Register Maps
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11
10
9
8
7
X
X
X
X
0
FRONT
PANEL
READY
(Read
Only)
12
11
10
9
8
X
X
X
X
X
6
5
4
POD
TRIG STATE
READY
(Read Only
(Read
Output of
Only)
Trigger Mux)
7
6
5
4
CTG 7
CTG 6
CTG 5
CTG 4
3
2
1
0
TRIG
COND 2 COND
COND 0
QUAL
1
3
2
1
CTG 3
CTG 2
CTG 1
CTG 0
0
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