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Trigger Delay (Read/Write)
The amount by which the minimum trigger latency is increased is N*6.25ns, where N is the 16-bit
unsigned integer in this register. There is a delay of up to 2
effect. Reading this location gives the last value written to it.
Address: Base + 1E
H
Bit #
15
Value
NOTE: The TTL/ECL translators used have a response time of approximately 2
3-14 Register Maps
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14
13
12
11
10
Additional Delay
0.00ns
6.25ns
12.50ns
.
.
.
µ
409.6
s
µ
s (see note below) before new values take
9
8
7
6
5
Trigger Delay
Register Value
0000
0001
0002
.
.
.
FFFF
4
3
2
1
0
µ
s.
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