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Status/Control # 1 (Write)
Address: Base + 06
H
Bit #
15
14
13
12
Value
X
X
X
X
NOTE: All bits are set to 0 after a hard or soft reset.
Bit Definitions
•
INVERT READY -- 0 to 1 = ready. 1 to 0 = ready.
•
CTG OE -- Control timing generator output enable. 1 = outputs enabled.
•
QDA REG. EN -- 1 = contents of register 1C
(see "External Input Direct Access" register, later in this chapter).
•
READ POD CAL. -- 1 = Pod CAL ROM can be read on "Q" inputs.
•
BRA MODE -- 0 = normal operation for MARKER sequence bit. 1 = MARKER bit becomes
branch function.
•
AUTO INCR. ENABLE -- 1 = Sequencer Memory Address (address = 10
sequence RAM is read (bit 5) or written (bit 4).
•
SEQUENCER WRITE ENABLE -- 1 in either MSB or LSB means that byte in sequencer cannot
be written to.
•
HSMA MODE -- 0 = normal high-speed memory addressing. 1 = read/write from VXI allowed.
•
HSMA/SEQ* -- 1 = high-speed memory address register (14
Set this bit along with Bit 1 to access the Truth Table RAM (16
RAM (18
), Stimulus Timing Generator RAM (24
H
(26
).
H
3-8 Register Maps
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11
10
9
8
INVERT
CTG
QDA
READ
READY
OE
REG.
POD
EN
CAL.
7
6
5
4
OSC
BRA
AUTO-INCR.
EN*
MODE
ENABLE
RD
WR
are placed permitted to drive certain module inputs
H
) replaces normal sequencer output.
H
), Control Timing Generator
H
), and Response Timing Generator RAM
H
3
2
1
0
SEQUENCER
HSMA
HSMA/
WRITE ENABLE
MODE
SEQ*
MSB
LSB
) increments after
H
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