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Status/Control # 1 (Read)
Bit 15 of this register is "don't-care" when writing and gives 0 when read. Bits 14-12 are "don't-care" when
writing but give status information when read. Bits 11-0 contain various configuration and mode bits and
give the last values written when read. Bits 13-0 are set to 0 by hard or soft reset; Bits 13-12 are also
cleared by the INIT command.
Address: Base + 06
H
Bit #
15
14
13
Value
0
POD
EOS BRKPT INVERT
PRE-
SENT
NOTE: All bits are set to 0 after a hard or soft reset.
Bit Definitions
•
Bit 14: POD PRESENT (1= there is a pod attached to the module)
•
Bit 13: EOS -- End of Sequence--(1 = the sequencer has encountered an end-of-sequence)
•
Bit 12: BRKPT -- Breakpoint-- (1 = the sequencer has encountered a breakpoint)
•
Bit 11: INVERT READY (1 = both front-panel and pod "Ready" inputs are active low)
•
Bit 10: CTG OE (1 = control timing generator outputs are enabled; 0 = the outputs are tri-state)
•
Bit 9: EIDA REG EN (1 = External Input Direct Access register is enabled, allowing it to drive
various external inputs)
•
Bit 8: READ POD (1 = normal pod operation is suspended and the module's control outputs and
Q inputs can be used to read the calibration ROM in the pod)
•
Bit 7: OSC EN* (0 = master oscillator is enabled)
•
Bit 6: BRANCH MODE (1 = the "Marker" bit in sequencer memory also serves as a branch point
for looping)
•
Bit 5: AUTO-INCR EN (RD) (1 = Sequencer Memory Address is post-incremented each time the
sequencer memory, register 12H, is read)
•
Bit 4: AUTO-INCR EN (WR) (1 = Sequencer Memory Address is post-incremented each time the
sequencer memory, register 12H, is written to)
•
Bit 3: WRITE EN* (MSB) (1 = most-significant byte of sequencer memory cannot be written to)
•
Bit 2: WRITE EN* (LSB) (1 = least-significant byte of sequencer memory cannot be written to)
•
Bit 1: HSMA MODE (1 = normal operation is suspended and the three timing generator memories
as well as the truth table memory can be addressed from the High-Speed Memory Address register)
•
Bit 0: HSMA/SEQ* (0 = normal operation; 1 = the High-Speed Memory Address register replaces
the normal sequencer output)
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12
11
10
9
CTG
EIDA
READ
READY
OE
REG
POD
EN
CAL.
8
7
6
5
OSC
BRA
AUTO-INCR.
EN*
MODE
ENABLE
RD
WR
4
3
2
1
SEQ.
SEQ.
HSMA
HSMA/
MSB
LSB
MODE
SEQ*
WE*
WE*
Register Maps 3-7
0
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