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Using the Write
Decoder Lines
Figure 2-2. Using the Write Decoder Line WP0
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You can use the eight Write Decoder lines (WP0 - WP7) as latch select lines
to expand for more output registers. Table 2-2 lists the Read/Write Decoder
Register Addresses and the corresponding WP and RP lines.
Table 2-2. Read/Write Decoder Lines and Register Addresses
WP / RP Line
Register Address
WP0/ RP0
20
in A24 Memory
h
WP1 / RP1
22
in A24 Memory
h
WP2 / RP2
24
in A24 Memory
h
WP3 / RP3
26
in A24 Memory
h
Figure 2-1 shows the timing required to write output data using one of the
Read/Write Decoder Registers and the corresponding WP Line. You only
have access to the DBEN*, LAT*, WPn, and BUSY control lines; the other
control line waveforms (SYSCLK, DS0*, etc.) are provided for reference
information only.
•
WPn has the same timing as LAT* when writing to the corresponding
register address.
•
There is no BUSY signal when writing to addresses other than14H in
A24 memory space.
•
MD15-MD0 are latched to latches on the rising edge of WPn.
Figure 2-2 shows an example of using the WP0 Decoder Line to serve as a
device latch signal.
74574 Register
A
Data Lines MD00 - MD15
H
WP0
To create an expanded register, write a data value to the appropriate
Read/Write Decoder Register. For example, to use the circuit in Figure 2-2,
you would write a 16-bit data value to the WP0 register (address 20
memory).
WP / RP Line
WP4 / RP4
WP5 / RP5
WP6 / RP6
WP7 / RP7
Q
1
Data Output Lines
Q
8
Using the Breadboard
Register Address
28
in A24 Memory
h
2A
in A24 Memory
h
2C
in A24 Memory
h
2E
in A24 Memory
h
in A24
h
21
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