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VXI Status/Control (Read)
Reading this register gives the module's VXI status.
Read Registers Address: Base + 04
Bit #
15
14
13
Value
0
MODID*
1
Bit Definitions
•
Bit 15: 0 (= A24/A32 inactive)
•
Bit 14: MODID* -- A 1 in this field indicates the device is not selected via the P2 MODID line. A
0 indicates that the device is selected by a high state on the P2 MODID line. Reset value is 1.(the
logical complement of the module's MODID input from the Slot-0 module)
•
Bits 13-8: 1
•
Bit 7: IEN* -- Interrupt Enabled. Enables the Timing I/O Module to interrupt on the VXI
backplane. Value of 1 = disabled; 0 = enabled. This bit is set (interrupt disabled) by a hard reset.
•
Bits 6-4: INTERRUPT LEVEL--indicate the setting of the interrupt switch:
001 = Level 1,
010 = Level 2,
.
.
111 = Level 7)
•
Bit 3: 1 (= Ready) Bit 2: 1 (= Passed) Bits 1-0: 1 (E1450 has no built-in self-test)
VXI Status/Control (Write)
Set the Timing Module VXI control bits.
Address: Base + 04
H
Bit #
15
14
13
Value
X
X
X
Bit Definitions
When writing to this register, all bits are "don't-care" except the following.
•
Bit 7: IEN* (0 = Enable interrupts; set to 1 by hard reset)
•
Bit 0: SOFT RESET Writing a 1 and then a 0 to this field performs a soft reset of the Timing I/O
Module. Notice that bit 7 is set and bit 0 is cleared by a hard reset but not by a soft reset.
3-6 Register Maps
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H
12
11
10
9
1
1
1
1
12
11
10
9
8
X
X
X
X
X
8
7
6
5
1
IEN*
See Below*
7
6
5
4
IEN*
X
X
X
4
3
2
1
0
1
1
1
1
3
2
1
0
X
X
X
Soft Reset
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