Table of Contents
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Index
A
Address guidelines, logical, 2-2
Address switch, logical, 2-2
Addresses, register, 3-1
B
Branch destination, 3-9
C
Cables, master/slave, 3-9
Calibration ROM , 3-10
Command register, 3-16
Configuration information, 2-2
Control output direct access, 3-13
Control TG memory data, 3-12
Control timing generator specifications, A-2
D
Definitions, register, 3-5
Destination, branch, 3-9
Device type (read only), 3-5
E
End-if-ready specifications, A-6
External input direct access, 3-13
E1450 Timing Module description, 1-1
E1453 Timing Pod description, 1-3
F
Fixturing techniques, recommended, 2-8
H
High-Speed memory address, 3-11
I
ID register (read only), 3-5
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Information, configuration, 2-2
Information, wiring, 2-5
L
Levels, output, A-2
Logical address guidelines, 2-2
Logical address switch, 2-2
M
Marker specifications, A-7
Master/Slave cables, 2-4
Miscellaneous specifications, A-7
O
Output control, trigger, 3-18
Output levels, A-2
R
Recommended fixturing techniques, 2-8
Register, ID, 3-5
Register addresses, 3-1
Register definitions, 3-5
Response TG memory data, 3-17
Response timing generator specifications, A-2
S
Sequencer memory address, 3-10
Sequencer memory data, 3-11
Sequencer specifications, A-1
Specifications, end-if-ready, A-6
Specifications, marker, A-7
Specifications, miscellaneous, A-7
Specifications, sequencer, A-1
Specifications, timebase, A-1
Specifications, trigger, A-3
Specifications, wait-for-condition, A-5
Status # 2, 3-15
Status/Control # 1, 3-7, 3-8
Status/Control, VXI, 3-6
Stimulus TG memory address, 3-17
Stimulus TG memory data, 3-16
Stimulus timing generator specifications, A-1
Subcycle period, 3-17
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