Ate Port Target Isp Port - Pin Routing (Relays Off) - Equinox Systems ISPnano I Series User Manual

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Datasheet of ISPNANO S3 KIT - ISP PORTABLE PROGRAMMER
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3.5 ATE Port
By default the RELAYs are OFF and the 'ATE Port' signals are routed to the 'Target ISP Port' pins
as detailed in the table below.
Target ISP ATE Port
Port Pin
Pin Number Number
1 + 2 13 + 14
3 + 4 No
connection
5 + 6 11 + 12
7a 8a
7b 8b
7c 8c
8a 7a
8b 7b
8c 7c
9 6
10 5
11 4
12 3
13 2
14 1
15 10
16 9
110
Target ISP Port – Pin routing (RELAYs OFF)
Programmer
Pin name
TARGET_VCC
EXT_VCC
PROG_GND
I2C SCL
•
PDI_CLK
•
TPI_CLK
•
I2C_SDA
•
XMEGA_PDI_DATA
•
ATTINY_TPI_DATA
•
OP6
Programmer I/O5
Programmer I/O4
Programmer I/O3
Programmer I/O2
Programmer I/O1
PROG_VPP
PROG_RESET
ISPnano Series Programmer - User Manual – V1.11 – 12
Notes
Target VCC
This pin should be connected to the Target
System Vcc.
Target External VCC
No connection required as EXT-VCC is
being used to control the RELAY coils.
Signal Ground Connection (1)
0V to which the programmer JTAG, SPI,
I2C, PDI, TPI signal lines are referenced
to.
I2C SCL clock signal
•
XMEGA PDI CLOCK Signal
•
ATtiny TPI CLOCK Signal
•
I2C SDA data signal
•
XMEGA PDI DATA Signal
•
ATtiny TPI DATA Signal
•
Spare Output (used for PDI / TPI)
Spare I/O pin
This pin is used for JTAG Target Systems
only.
This pin can be used for JTAG or SPI
Target Systems.
This pin can be used for JTAG, SPI,
UART, XMEGA PDI and ATtiny TPI Target
Systems.
This pin can be used for JTAG, SPI or
UART Target Systems.
Vpp Voltage
Target RESET control pin
th
May 2011