Appendix 4 - Ispnano Series 3 Ate; Overview - Equinox Systems ISPnano I Series User Manual

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Datasheet of ISPNANO S3 KIT - ISP PORTABLE PROGRAMMER
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Appendix 4 – ISPnano Series 3 ATE

1.0 Overview

The "ISPnano Series III ATE" is a state-of-the-art ISP Programmer designed for high-speed In-
System Programming (ISP) of FLASH Microcontrollers and Serial Memory devices in a production
environment. It has been specially developed to allow simple integration with Automatic Test
Equipment (ATE) systems and In-Circuit Testers (ICTs) used in high-volume production systems.
The programmer supports automated relay switching of all Target System programming and power
signal lines between an external ATE / ICT system and the programmer. This allows it to be
completely out-of-circuit during normal ATE testing operation. A dedicated 'ATE Interface' also allows
the ATE / ICT to control the operation of the programmer in 'Standalone Mode' (no PC required).
Features
Integrated 'ISPnano Series 3' programmer (see separate features for this module)
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Compact enclosure featuring integrated programmer and relay switching module
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All programmer I/O signal lines are isolated from both the Target System (UUT) and ATE / ICT
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via relays
All power lines (Target Vcc, Target Vpp and GROUND) are independently switched via relays.
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The ATE / ICT is routed to the Target System (UUT) by default so the programmer is
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completely isolated from the UUT.
When a programming operation starts, the Target System (UUT) ISP I/O and power signals
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are automatically switched to the programmer and the ATE / ICT is then completely isolated
from the programmer.
At the end of a programming operation, the Target System (UUT) is automatically re-
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connected to the ATE / ICT.
Simple integration with ATE / ICT as the programmer controls the relay switching
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'RELAYS ON' indicator signals when the programmer is connected to the Target System
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(UUT)
An external +12V supply is required to power the relay coils (Connect to EXT-VCC connector
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on the programmer)
Supports signal routing of an external 'JTAG Boundary Scan Tester' via the ATE Port to the
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Target System (UUT).