HP 9000 300 Series Hardware Configuration Manual page 116

• RD. This mode causes the data to be clocked into the input register when
the register is read. It accomplishes this by clocking the leading edge of the
output enable signal of the register.
• BSY. This mode clocks the data into the data input register by a
ready-to-busy transition of the PFLG line. This transition also clears the
PCTL line.
• RDY. This mode clocks the data into the data input register by a
busy-to-ready transition of the PFLG line.
Setting the Option Select Switches. Refer to Table 10-3 and find the Option
Select switches labeled Ul. If you will be connecting an HP 9884A Paper Tape
Punch to this interface, set all of these switches to 1.
Table 10-3.
Switch Function Logic 1 Logic 0
Position (Switch (Switch
Name Open) Closed)
DOUT Invert
Low
=
1 Low
=
0
Data Out
High
=
0 High
=
1
DIN Invert
Low
=
1 Low
=
0
Data In High
=
0 High
=
1
HSHK
Full/Pulse
Full Pulse
Handshake
PSTS Invert Low
=
OK Low
=
OK
PSTS
High
=
OK High
=
OK
PFLG Invert
Low
=
Rdy Low
=
Bsy
PFLG High
=
Bsy High
=
Rdy
PCTL Invert
Low
=
set Low
=
Clr
PCTL
High
=
Clr High
=
Set
Configuring Popular Accessory Cards 10-7
10