Control Register
A single register, SMOD, is used for overall control of the internal clocks within the devices.
SMOD Register
Bit
7
Name
CKS2
R/W
R/W
POR
0
Bit 7~5
CKS2~CKS0: The system clock selection when HLCLK is "0"
000: f
001: f
010: f
011: f
100: f
101: f
110: f
111: f
These three bits are used to select which clock is used as the system clock source. In
addition to the system clock source, which can be either the LXT or LIRC, a divided
version of the high speed system oscillator can also be chosen as the system clock
source.
Bit 4
FSTEN: Fast Wake-up Control (only for HXT)
0: Disable
1: Enable
This is the Fast Wake-up Control bit which determines if the f
initially used after the devices wake up. When the bit is high, the f
be used as a temporary system clock to provide a faster wake up time as the f
is available.
Bit 3
LTO: Low speed system oscillator ready flag
0: Not ready
1: Ready
This is the low speed system oscillator ready flag which indicates when the low speed
system oscillator is stable after power on reset or a wake-up has occurred. The flag
will be low when in the SLEEP0 Mode but after a wake-up has occurred, the flag will
change to a high level after 1024 clock cycles if the LXT oscillator is used and 1~2
clock cycles if the LIRC oscillator is used.
Bit 2
HTO: High speed system oscillator ready flag
0: Not ready
1: Ready
This is the high speed system oscillator ready flag which indicates when the high speed
system oscillator is stable. This flag is cleared to "0" by hardware when the devices are
powered on and then changes to a high level after the high speed system oscillator is
stable. Therefore this flag will always be read as "1" by the application program after
devices power-on. The flag will be low when in the SLEEP or IDLE0 Mode but after
a wake-up has occurred, the flag will change to a high level after 1024 clock cycles if
the HXT oscillator is used and after 15~16 clock cycles if the ERC or HIRC oscillator
is used.
Rev. 1.40
TinyPower
Flash MCU with OPA & Comparators
TM
6
5
4
CKS1
CKS0
FSTEN
R/W
R/W
R/W
0
0
0
(f
or f
)
L
LXT
LIRC
(f
or f
)
L
LXT
LIRC
/64
H
/32
H
/16
H
/8
H
/4
H
/2
H
44
HT45F23A/HT45F24A
3
2
1
LTO
HTO
IDLEN
R
R
R/W
0
0
1
clock source is
SUB
clock source can
SUB
March 29, 2019
0
HLCLK
R/W
1
clock
SUB
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