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Features
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Operating voltage: 2.0V~3.6V
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8 bidirectional I/O lines and 8 input lines
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Two external interrupt input
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One 8-bit programmable timer/event counter
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LCD driver with 21´2, 21´3 or 20´4 segments
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2K´14 program memory
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96´8 data memory RAM
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Real Time Clock (RTC)
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8-bit prescaler for RTC
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One carrier output (1/2 or 1/3 duty)
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Software LCD, RTC control
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On-chip RC and 32768Hz crystal oscillator
General Description
The HT49RA0/HT49CA0 are 8-bit high performance,
RISC architecture microcontroller devices specifically
designed for multiple I/O control product applications.
The mask version HT49CA0 is fully pin and functionally
compatible with the OTP version HT49RA0 device.
The advantages of low power consumption, I/O
flexibility, timer functions, oscillator options, watchdog
Rev. 1.50
Remote Type 8-Bit MCU
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Watchdog Timer
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HALT function and wake-up feature reduce power
consumption
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4-level subroutine nesting
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Bit manipulation instruction
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14-bit table read instruction
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Up to 1ms instruction cycle with 4MHz system clock
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63 powerful instructions
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All instructions in 1 or 2 machine cycles
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Low voltage reset/detector function
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64-pin LQFP package
timer, HALT and wake-up functions, as well as low cost,
enhance the versatility of this device to suit a wide range
of application possibilities such as industrial control,
consumer products, and particularly suitable for use in
products such as infrared LCD remote controllers and
various subsystem controllers.
1
HT49RA0/HT49CA0
with LCD
March 20, 2014
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Related Manuals for Holtek HT49RA0
Summary of Contents for Holtek HT49RA0
- Page 1 The mask version HT49CA0 is fully pin and functionally consumer products, and particularly suitable for use in compatible with the OTP version HT49RA0 device. products such as infrared LCD remote controllers and various subsystem controllers.
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Page 2: Block Diagram
HT49RA0/HT49CA0 Block Diagram I n t e r r u p t C i r c u i t S Y S T M R C S Y S R T C I n t e r r u p t... - Page 3 HT49RA0/HT49CA0 Pin Description Pin Name Options Description Bidirectional 8-bit input/output port with pull-high resistors. Each bit can ¾ PA0~PA7 be determined as NMOS output or Schmitt trigger input by software in- structions. PB0/INT0 8-bit Schmitt trigger input port with pull-high resistors. Eash bit can be PB1/INT1 configured as a wake-up input by code option.
- Page 4 HT49RA0/HT49CA0 Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Standby Current No load, system HALT ¾ STB3 =WDT RC OSC) LCD On at HALT, C type Input Low Voltage for I/O ¾ ¾ 0.3V Ports, TMR, INT0 and INT1 Input High Voltage for I/O ¾...
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Page 5: Functional Description
HT49RA0/HT49CA0 Functional Description Execution Flow After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by The system clock is derived from RC oscillator. It is inter- one. The PC then points to the memory word containing nally divided into four non-overlapping clocks. - Page 6 HT49RA0/HT49CA0 · Location 014H When a control transfer takes place, an additional dummy cycle is required. Location 014H is reserved for the real time clock inter- rupt service program. If a real time clock interrupt oc- Program Memory - ROM curs, and the interrupt is enabled, and the stack is not full, the program begins execution at location 014H.
- Page 7 HT49RA0/HT49CA0 Stack Register - STACK I n d i r e c t A d d r e s s i n g R e g i s t e r 0 0 0 H M P 0 0 1 H...
- Page 8 HT49RA0/HT49CA0 Status Register - STATUS Once an interrupt subroutine is serviced, other inter- rupts are all blocked (by clearing the EMI bit). This The status register (0AH) is of 8 bits wide and contains, scheme may prevent any further interrupt nesting. Other...
- Page 9 HT49RA0/HT49CA0 The internal Timer/Event Counter interrupt is initialized Interrupts occurring in the interval between the rising by setting the Timer/Event Counter interrupt request flag edges of two consecutive T2 pulses are serviced on the (TF;bit 6 of INTC0), which is normally caused by a timer latter of the two T2 pulses if the corresponding interrupts overflow.
- Page 10 HT49RA0/HT49CA0 It is recommended that a program not use the ²CALL Oscillator Configuration subroutine² within the interrupt subroutine. It¢s because An external resistor between OSC1 and VSS in needed interrupts often occur in an unpredictable manner or re- and the resistance is about 12kW. The RC oscillator quire to be serviced immediately in some applications.
- Page 11 HT49RA0/HT49CA0 Watchdog Timer - WDT (TBF; bit 4 of INTC1) is set. But if the interrupt is en- abled, and the stack is not full, a subroutine call to loca- The WDT clock source is implemented by a dedicated tion 10H occurs.
- Page 12 HT49RA0/HT49CA0 Power Down Operation - HALT Reset The HALT mode is initialized by the ²HALT² instruction There are three ways in which reset may occur. · and results in the following. RES is reset during normal operation · · The system oscillator turns off but the WDT OSC...
- Page 13 HT49RA0/HT49CA0 V D D 0 . 0 1 m F R E S S S T 1 0 0 k W 1 0 0 k W S S T T i m e - o u t R E S...
- Page 14 HT49RA0/HT49CA0 Timer/Event Counter mode can be used to count the high or low level duration of the external signal (TMR), and the counting is based One timer/event counters are implemented in the devices. on the internal selected clock source. It contains an 8-bit programmable count-up counter.
- Page 15 To enable the counting operation, the Timer ON bit (TON: bit 4 of TMRC) should be set to 1. In the pulse The HT49RA0/HT49CA0 provides a carrier output width measurement mode, the TON is automatically which shares the pin with PC0. It can be selected to be a cleared after the measurement cycle is completed.
- Page 16 After chip reset, PA, PB and PC remain at a high level in- HT49RA0/HT49CA0, labeled as PA, PB and PC which put line. are mapped to [12H], [14H], [16H] of the RAM respec- Each bit of PA and PC output latches can be set or tively.
- Page 17 HT49RA0/HT49CA0 P u l l - H i g h C o n t r o l B i t O p t i o n D a t a B u s W r i t e C o n t r o l R e g i s t e r...
- Page 18 HT49RA0/HT49CA0 D u r i n g a R e s e t P u l s e C O M 0 , C O M 1 , C O M 2 V S S A l l L C D d r i v e r o u t p u t s...
- Page 19 HT49RA0/HT49CA0 C O M 0 V S S C O M 1 V S S C O M 2 V S S C O M 3 V S S L C D s e g m e n t s O N...
- Page 20 HT49RA0/HT49CA0 Low Voltage Reset/Detector Functions There is a low voltage detector (LVD) and a low voltage reset circuit (LVR) implemented in the microcontroller. These two functions can be enabled/disabled by options. Once the LVD options is enabled, the user can use the RTCC.3 to enable/disable (1/0) the LVD circuit and read the LVD detector status (0/1) from RTCC.5;...
- Page 21 HT49RA0/HT49CA0 The microcontroller provides a low voltage reset circuit The relationship between V and V is shown below. in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 3 . 6 V 0.9V~V...
- Page 22 HT49RA0/HT49CA0 Options The following shows the options in the devices. All these options should be defined in order to ensure proper system functioning. Item Options I/O Options PB0~PB7: wake-up enable or disable (bit option) PC0: CMOS output or carrier output (bit option)
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Page 23: Application Circuits
HT49RA0/HT49CA0 Application Circuits V D D R e s e t 1 0 0 k W C i r c u i t 0 . 1 m F R E S P A 0 ~ P A 7 0 . 1 m F... - Page 24 HT49RA0/HT49CA0 Example P A 2 P A 1 P A 0 P A 3 P B 3 P A 4 P B 2 P A 5 P B 1 P B 7 P B 0 P B 6 P B 5...
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Page 25: Instruction Set
For easier understanding of the various instruction The standard logical operations such as AND, OR, XOR codes, they have been subdivided into several func- and CPL all have their own instruction within the Holtek tional groupings. microcontroller instruction set. As with the case of most... - Page 26 In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² in- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to...
- Page 27 HT49RA0/HT49CA0 Mnemonic Description Cycles Flag Affected Rotate RRA [m] Rotate Data Memory right with result in ACC None Note RR [m] Rotate Data Memory right None RRCA [m] Rotate Data Memory right through Carry with result in ACC Note RRC [m]...
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Page 28: Instruction Definition
HT49RA0/HT49CA0 Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ¬ ACC + [m] + C... - Page 29 HT49RA0/HT49CA0 CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address.
- Page 30 HT49RA0/HT49CA0 CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ¬ [m] Operation Affected flag(s) CPLA [m]...
- Page 31 HT49RA0/HT49CA0 INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. [m] ¬ [m] + 1 Operation Affected flag(s) INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu- lator.
- Page 32 HT49RA0/HT49CA0 OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²OR² x Operation Affected flag(s)
- Page 33 HT49RA0/HT49CA0 RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0.
- Page 34 HT49RA0/HT49CA0 SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
- Page 35 HT49RA0/HT49CA0 SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
- Page 36 HT49RA0/HT49CA0 SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 « [m].7 ~ [m].4 Operation Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
- Page 37 HT49RA0/HT49CA0 XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²XOR² [m] Operation Affected flag(s)
- Page 38 HT49RA0/HT49CA0 Package Information Note that the package information provided here is for consultation purposes only. As this information may be updated at regular intervals users are reminded to consult the Holtek website for the latest version of the Package/Carton Information.
- Page 39 HT49RA0/HT49CA0 64-pin LQFP (7mm´7mm) Outline Dimensions Dimensions in inch Symbol Min. Nom. Max. ¾ ¾ 0.354 BSC ¾ ¾ 0.276 BSC ¾ ¾ 0.354 BSC ¾ ¾ 0.276 BSC ¾ ¾ 0.016 BSC 0.005 0.007 0.009 0.053 0.055 0.057 ¾...
- Page 40 Holtek¢s products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification.
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