I 2 C Bus Start Signal - Holtek HT45F23A Manual

HT45F23A/HT45F24A
TinyPower Flash MCU with OPA & Comparators
TM
I C Bus Start Signal
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The START signal can only be generated by the master device connected to the I
the slave device. This START signal will be detected by all devices connected to the I
detected, this indicates that the I
condition occurs when a high to low transition on the SDA line takes place when the SCL line
remains high.
Slave Address
The transmission of a START signal by the master will be detected by all devices on the I
To determine which slave device the master wishes to communicate with, the address of the slave
device will be sent out immediately following the START signal. All slave devices, after receiving
this 7-bit address data, will compare it with their own 7-bit slave address. If the address sent out by
the master matches the internal address of the microcontroller slave device, then an internal I
interrupt signal will be generated. The next bit following the address, which is the 8th bit, defines
the read/write status and will be saved to the SRW bit of the SIMC1 register. The slave device will
then transmit an acknowledge bit, which is a low level, as the 9th bit. The slave device will also set
the status flag HAAS when the addresses match.
As an I C bus interrupt can come from two sources, when the program enters the interrupt
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subroutine, the HAAS bit should be examined to see whether the interrupt source has come from
a matching slave address or from the completion of a data byte transfer. When a slave address is
matched, the device must be placed in either the transmit mode and then write data to the SIMD
register, or in the receive mode where it must implement a dummy read from the SIMD register to
release the SCL line.
Rev. 1.40
S t a r t
S E T S I M [ 2 : 0 ] = 1 1 0
S E T S I M E N
W r i t e S l a v e
A d d r e s s t o S I M A
N o I C B u s
2
I n t e r r u p t = ?
C L R E S I M
P o l l S I M F t o d e c i d e
w h e n t o g o t o I C B u s I S R
2
G o t o M a i n P r o g r a m
I 2 C Bus Initialisation Flow Chart
C bus is busy and therefore the HBB bit will be set. A START
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101
Y e s
S E T E S I M
W a i t f o r I n t e r r u p t
G o t o M a i n P r o g r a m
C bus and not by
2
C bus. When
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March 29, 2019
C bus.
2
C bus
2