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Technical Document
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Tools Information
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FAQs
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Application Note
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HA0017E Controlling the Read/Write Function of the HT24 Series EEPROM Using the HT49 Series MCUs
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HA0024E Using the RTC in the HT49 MCU Series
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HA0025E Using the Time Base in the HT49 MCU Series
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HA0026E Using the I/O Ports on the HT49 MCU Series
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HA0027E Using the Timer/Event Counter in the HT49 MCU Series
Features
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Operating voltage:
f
=4MHz: 2.2V~5.5V
SYS
f
=8MHz: 3.3V~5.5V
SYS
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8 input lines and 7 output lines
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16 bidirectional I/O lines
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Two external interrupt inputs
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One 8-bit and two 16-bit programmable timer/event
counters with PFD - programmable frequency divider
function
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LCD driver with 48´2, 48´3 or 47´4 segments
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16K´16 program memory
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576´8 data memory RAM
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Real Time Clock - RTC
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RTC 8-bit prescaler
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Watchdog Timer
General Description
These devices are 8-bit, high performance, RISC archi-
tecture microcontrollers specifically designed for a wide
range of LCD applications. The mask version, the
HT49CU80, is fully pin and functionally compatible with
the OTP version HT49RU80 device.
The advantages of low power consumption, I/O flexibil-
ity, programmable frequency divider, timer functions,
oscillator options, power-down and wake-up functions
Rev. 1.10
HT49RU80/HT49CU80
LCD Type 8-Bit MCU
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Buzzer output
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On-chip crystal, RC and 32768Hz crystal oscillator
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HALT function and wake-up feature reduce power
consumption
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16-level subroutine nesting
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UART - Universal Asynchronous Receiver
Transmitter
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Bit manipulation instruction
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16-bit table read instruction
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Up to 0.5ms instruction cycle with 8MHz system clock
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63 powerful instructions
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All instructions executed within 1 or 2 machine cycles
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Low voltage reset/detector functions
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100-pin QFP package
and buzzer driver in addition to a flexible and
configurable LCD interface, enhance the versatility of
these devices to control a wide range of LCD-based ap-
plication possibilities such as measuring scales, elec-
tronic multimeters, gas meters, timers, calculators,
remote controllers and many other LCD-based indus-
trial and home appliance applications.
1
March 2, 2007
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Related Manuals for Holtek HT49RU80
Summary of Contents for Holtek HT49RU80
- Page 1 LCD-based ap- HT49CU80, is fully pin and functionally compatible with plication possibilities such as measuring scales, elec- the OTP version HT49RU80 device. tronic multimeters, gas meters, timers, calculators, remote controllers and many other LCD-based indus- The advantages of low power consumption, I/O flexibil- trial and home appliance applications.
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Page 2: Block Diagram
HT49RU80/HT49CU80 Block Diagram Rev. 1.10 March 2, 2007... -
Page 3: Pin Assignment
HT49RU80/HT49CU80 Pin Assignment H T 4 9 R U 8 0 / H T 4 9 C U 8 0 1 0 0 Q F P - A Rev. 1.10 March 2, 2007... - Page 4 HT49RU80/HT49CU80 Pad Description Pad Name Options Description Bidirectional 8-bit input/output port. Each pin on this port can be configured as a wake-up input by a configuration option. Configuration options deter- PA0/BZ Wake-up mine whether pins PA0~PA3 are configured as CMOS outputs or NMOS in-...
- Page 5 HT49RU80/HT49CU80 Absolute Maximum Ratings -0.3V to V Supply Voltage ......V +6.0V Storage Temperature ......-50°C to 125°C -0.3V to V Input Voltage......V +0.3V Operating Temperature......-40°C to 85°C Total ..............150mA Total............-100mA Total Power Dissipation ........500mW Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device.
- Page 6 HT49RU80/HT49CU80 Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Input Low Voltage for I/O Ports, ¾ ¾ ¾ 0.3V TMR0, TMR1, TMR2, INT0 and INT1 Input High Voltage for I/O Ports, ¾ ¾ ¾ 0.7V TMR0, TMR1, TMR2, INT0 and INT1 ¾...
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Page 7: Functional Description
HT49RU80/HT49CU80 Functional Description Execution Flow specify a maximum of 16384 addresses. The system clock is derived from either a crystal or an After accessing a program memory word to fetch an in- RC oscillator or a 32768Hz crystal oscillator. It is inter- struction code, the value of the PC is incremented by ²1². - Page 8 HT49RU80/HT49CU80 The lower byte of the PC, known as PCL, is a readable that the desired program memory bank is addressed. If and writeable register. Moving data into the PCL performs a return from a CALL instruction or an interrupt is exe- a short jump.
- Page 9 HT49RU80/HT49CU80 · Table location General Purpose Data Memory is subdivided into three Any location in the program memory can be used as banks, Banks 0, 2 and 3 each of which has a capacity of look-up tables. The instructions ²TABRDC [m]² (page 192 ´...
- Page 10 HT49RU80/HT49CU80 Arithmetic and Logic Unit - ALU This circuit performs 8-bit arithmetic and logic opera- tions and provides the following functions: · Arithmetic operations - ADD, ADC, SUB, SBC, DAA · Logical operations - AND, OR, XOR, CPL · Rotations - RL, RR, RLC, RRC ·...
- Page 11 HT49RU80/HT49CU80 Bit No. Label Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a rotate through carry instruction.
- Page 12 HT49RU80/HT49CU80 Bit No. Label Function Controls the master (global) interrupt (1=enable; 0=disable) EEI0 Controls the external interrupt 0 (1=enable; 0=disable) EEI1 Controls the external interrupt 1 (1=enable; 0=disable) ET0I Controls the Timer/Event Counter 0 overflow interrupt (1=enable; 0=disable) EIF0 External interrupt 0 request flag (1=active; 0=inactive) EIF1 External interrupt 1 request flag (1=active;...
- Page 13 HT49RU80/HT49CU80 Oscillator Configuration the crystal and to get a frequency reference, but two ex- ternal capacitors connected between OSC1/OSC2 and These devices contain three kinds of system clocks, an ground are required. RC oscillator, a crystal oscillator and a 32768Hz crystal...
- Page 14 HT49RU80/HT49CU80 Time Base If the WDT clock source chooses the internal WDT oscil- lator as its clock source, the time-out period may vary The time base offers a periodic time-out period to gener- with temperature, VDD, and process variations. If the ate a regular internal interrupt.
- Page 15 HT49RU80/HT49CU80 Power Down Mode - HALT If a wake-up event occurs, it takes 1024 t system clock periods to resume normal operation. In other The power down mode is initialised when a ²HALT² in- words, a dummy period is inserted after the wake-up. If struction is executed and results in the following.
- Page 16 HT49RU80/HT49CU80 input allows external events to be counted, time intervals or pulse widths to be measured, or an accurate time base to be generated. Using the internal clock al- lows an accurate time base to be generated. The Timer/Event Counter 2 contains a 16-bit program- mable count-up counter whose clock may be sourced from an external source or an internal clock source.
- Page 17 HT49RU80/HT49CU80 The register states are summarised below: Reset WDT Time-out RES Reset RES Reset WDT Time-out Register (Power On) (Norma Operation) (Normal Operation) (HALT) (HALT)* xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu xxxx xxxx uuuu uuuu uuuu uuuu...
- Page 18 HT49RU80/HT49CU80 ternal selected clock source. Finally, the pulse width timer/event counter is turned on, data written to the measurement mode can be used to count the high or timer/event counter is kept only in the timer/event coun- low level duration of the external signal (TMR0/TMR1/ ter preload register.
- Page 19 HT49RU80/HT49CU80 Timer/Event Counter 0 Timer/Event Counter 1 Timer/Event Counter 2 PFD Source Option Rev. 1.10 March 2, 2007...
- Page 20 HT49RU80/HT49CU80 Bit No. Label Function ¾ Unused bit, read as ²0² Defines the TMR0 active edge of the timer/event counter: In Event Counter Mode (T0M1,T0M0)=(0,1): 1= count on falling edge; 0= count on rising edge In Pulse Width measurement mode (T0M1,T0M0)=(1,1): 1= start counting on the rising edge, stop on the falling edge;...
- Page 21 HT49RU80/HT49CU80 Input/Output Ports There are three function pins that share with the PA port: PA0/BZ, PA1/BZ and PA3/PFD. There are two 8-bit bidirectional input/output ports, PA The BZ and BZ are buzzer driving output pair and the and PC and one 8-bit input PB and one 7-bit output PD.
- Page 22 HT49RU80/HT49CU80 PA0~PA3 Input/Output Ports PA4~PA7 Input/Output Ports PB Input Port PC0/TX Input/Output Port Rev. 1.10 March 2, 2007...
- Page 23 HT49RU80/HT49CU80 PC1/RX Input/Output Port PC2~PC7 Input/Output Ports PD Output Port Rev. 1.10 March 2, 2007...
- Page 24 HT49RU80/HT49CU80 LCD Display Memory The device provides an area of embedded data memory for the LCD display. This area is located from 40H to 6FH in Bank 1 of the data memory. The bank pointer, BP, is used to switch between the general purpose data memory and the LCD display memory.
- Page 25 HT49RU80/HT49CU80 D u r i n g a r e s e t p u l s e N o r m a l o p e r a t i o n m o d e H A L T M o d e LCD Driver Output (1/3 Duty, 1/2 Bias, R/C Type) Rev.
- Page 26 HT49RU80/HT49CU80 The LCD driver requires a clock source for proper operation. The LCD clock source is sourced from the general pur- pose prescaler whose frequency value is determined by configuration options. The LCD clock frequency should be se- lected to be as close to 4kHz as possible. The LCD clock frequency options are listed in the following table.
- Page 27 I/O pin, if the pin is not configured as a receiver, which occurs The HT49RU80/HT49CU80 devices contain an inte- if the RXEN bit in the UCR2 register is equal to zero.
- Page 28 HT49RU80/HT49CU80 · USR register RXIF flag is cleared when the USR register is read The USR register is the status register for the UART, with RXIF set, followed by a read from the RXR reg- which can be read by the program to determine the ister, and if the RXR register has no data available.
- Page 29 HT49RU80/HT49CU80 ¨ used, if the bit is equal to ²0² then only one stop bit is PERR The PERR flag is the parity error flag. When this used. read only flag is ²0² it indicates that a parity error ¨...
- Page 30 HT49RU80/HT49CU80 · to ²0² and if the MCU is in the Power Down Mode, UCR2 register The UCR2 register is the second of the two UART any edge transitions on the RX pin will not wake-up control registers and serves several purposes. One of the device.
- Page 31 HT49RU80/HT49CU80 ¨ TXEN By programming the BRGH bit which allows selection The TXEN bit is the Transmitter Enable Bit. When of the related formula and programming the required this bit is equal to ²0² the transmitter will be disabled value in the BRG register, the required baud rate can be setup.
- Page 32 HT49RU80/HT49CU80 Baud Rates for BRGH=1 Baud Rate =8MHz =7.159MHz =4MHz =3.579545MHz K/BPS Kbaud Error Kbaud Error Kbaud Error Kbaud Error ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 1.202 0.16 1.203...
- Page 33 HT49RU80/HT49CU80 ¨ Transmitting data Start Data Address Parity Stop When the UART is transmitting data, the data is Bits Bits Bits shifted on the TX pin from the shift register, with the Example of 8-bit Data Formats least significant bit first. In the transmit mode, the TXR register forms a buffer between the internal bus and the transmitter shift register.
- Page 34 HT49RU80/HT49CU80 ¨ Transmit break Set the RXEN bit to ensure that the RX pin is used If the TXBRK bit is set then break characters will be as a UART receiver pin and not as an I/O pin. sent on the next transmission. Break character At this point the receiver will be enabled which will transmission consists of a start bit, followed by 13´...
- Page 35 HT49RU80/HT49CU80 ¨ Receiver interrupt No interrupt will be generated. However this bit The read only receive interrupt flag RXIF in the USR rises at the same time as the RXIF bit which itself register is set by an edge generated by the receiver.
- Page 36 HT49RU80/HT49CU80 the UCR2 register is set. The two transmitter interrupt exclusive functions. Therefore if the address detect conditions have their own corresponding enable bits, mode is enabled, then to ensure correct operation, the while the two receiver interrupt conditions have a parity function should be disabled by resetting the par- shared enable bit.
- Page 37 HT49RU80/HT49CU80 Configuration Options The following shows the options in the device. All these options should be defined in order to ensure proper functioning system.Configuration options refer to certain options within the MCU that are programmed into the device during the programming process.
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Page 38: Application Circuits
HT49RU80/HT49CU80 Application Circuits R C S y s t e m O s c i l l a t o r S e e r i g h t s i d e C r y s t a l S y s t e m... - Page 39 HT49RU80/HT49CU80 Instruction Set Summary Instruction Flag Mnemonic Description Cycle Affected Arithmetic ADD A,[m] Add data memory to ACC Z,C,AC,OV ADDM A,[m] Add ACC to data memory Z,C,AC,OV ADD A,x Add immediate data to ACC Z,C,AC,OV ADC A,[m] Add data memory to ACC with carry...
- Page 40 HT49RU80/HT49CU80 Instruction Flag Mnemonic Description Cycle Affected Branch JMP addr Jump unconditionally None SZ [m] Skip if data memory is zero None SZA [m] Skip if data memory is zero with data movement to ACC None SZ [m].i Skip if bit i of data memory is zero None SNZ [m].i...
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Page 41: Instruction Definition
HT49RU80/HT49CU80 Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added si- multaneously, leaving the result in the accumulator. ACC ¬ ACC+[m]+C Operation Affected flag(s) ¾... - Page 42 HT49RU80/HT49CU80 AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND op- eration. The result is stored in the accumulator. ACC ¬ ACC ²AND² [m] Operation Affected flag(s) ¾...
- Page 43 HT49RU80/HT49CU80 CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. [m].i ¬ 0 Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared.
- Page 44 HT49RU80/HT49CU80 CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged.
- Page 45 HT49RU80/HT49CU80 HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared.
- Page 46 HT49RU80/HT49CU80 MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. ACC ¬ x Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory...
- Page 47 HT49RU80/HT49CU80 Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter ¬ Stack Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator...
- Page 48 HT49RU80/HT49CU80 RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re- places the carry bit; the original carry flag is rotated into the bit 0 position.
- Page 49 HT49RU80/HT49CU80 RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator.
- Page 50 HT49RU80/HT49CU80 SET [m] Set data memory Description Each bit of the specified data memory is set to 1. [m] ¬ FFH Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1.
- Page 51 HT49RU80/HT49CU80 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ¬ ACC+[m]+1 Operation Affected flag(s) ¾ ¾ Ö Ö Ö Ö...
- Page 52 HT49RU80/HT49CU80 SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles).
- Page 53 HT49RU80/HT49CU80 XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu- sive_OR operation and the result is stored in the accumulator. ACC ¬ ACC ²XOR² [m] Operation Affected flag(s) ¾...
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Page 54: Package Information
HT49RU80/HT49CU80 Package Information 100-pin QFP (14´20) Outline Dimensions Dimensions in mm Symbol Min. Nom. Max. ¾ 18.50 19.20 ¾ 13.90 14.10 ¾ 24.50 25.20 ¾ 19.90 20.10 ¾ ¾ 0.65 ¾ ¾ 0.30 ¾ 2.50 3.10 ¾ ¾ 3.40 ¾... - Page 55 Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used...
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