Spi Registers - Holtek HT45F23A Manual

The SPI function in this device offers the following features:
• Full duplex synchronous data transfer
• Both Master and Slave modes
• LSB first or MSB first data transmission modes
• Transmission complete flag
• Rising or falling active clock edge
• WCOL and CSEN bit enabled or disable select
C K P O L B b i t
S C K P i n
T i m e r 0 o u t p u t / 2
S C S P i n
The status of the SPI interface pins is determined by a number of factors such as whether the device
is in the master or slave mode and upon the condition of certain control bits such as CSEN and
SIMEN.
There are several configuration options associated with the SPI interface. One of these is to
enable the SIM function which selects the SIM pins rather than normal I/O pins. Note that if the
configuration option does not select the SIM function then the SIMEN bit in the SIMC0 register will
have no effect. Another two SPI configuration options determine if the CSEN and WCOL bits are to
be used.

SPI Registers

There are three internal registers which control the overall operation of the SPI interface. These are
the SIMD data register and two registers SIMC0 and SIMC2. Note that the SIMC1 register is only
used by the I C interface.
2
Register
Name
7
SIMC0 SIM2
SIMD D7
SIMC2 D7
The SIMD register is used to store the data being transmitted and received. The same register is used
by both the SPI and I
be transmitted must be placed in the SIMD register. After the data is received from the SPI bus, the
device can read it from the SIMD register. Any transmission or reception of data from the SPI bus
must be made via the SIMD register.
Rev. 1.40
TinyPower Flash MCU with OPA & Comparators
TM
S I M D
T x / R x S h i f t R e g i s t e r
C l o c k
C K E G b i t
E d g e / P o l a r i t y
C o n t r o l
S t a t u s
f
S Y S
C l o c k
f
S U B
S o u r c e S e l e c t
C o n f i g u r a t i o n
C S E N b i t
O p t i o n
E n a b l e / D i s a b l e
6 5
SIM1 SIM0 PCKEN
D6 D5 D4
D6 CKPOLB CKEG
SIM Registers List
C functions. Before the device writes data to the SPI bus, the actual data to
2
90
HT45F23A/HT45F24A
D a t a B u s
S D I P i n
S D O P i n
E n a b l e / D i s a b l e
B u s y
C o n f i g u r a t i o n
W C O L F l a g
O p t i o n
T R F F l a g
Bit
4 3 2
PCKP1 PCKP0 SIMEN
D3 D2
MLS CSEN WCOL
1 0
—
D1 D0
TRF
March 29, 2019