Holtek HT46R74D-1 Technical Document

Dual slope a/d type mcu with lcd

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Features

Operating voltage:

= 4MHz: 2.2V~5.5V

SYS

= 8MHz: 3.3V~5.5V

SYS

10 bidirectional I/O lines and two ADC inputs

Two external interrupts inputs shared with I/O lines

One 8-bit and one 18-bit programmable timer/event

counter with overflow interrupt and pre-scaler

LCD driver with 15´4, 16´3 or 16´2 segments

4K´15 program memory with partial lock function

96´8 data memory RAM

Single differential input channel dual slope Analog to

Digital Converter with Operational Amplifier.

Watchdog Timer with regulator power

Buzzer output

External 32768Hz RTC oscillator

General Description

The HT46R74D-1 is an 8-bit high performance, RISC

architecture microcontroller device specifically de-

signed for A/D with LCD applications that interface di-

rectly to analog signals, such as those from sensors.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, Dual slope A/D

Rev. 1.40

Dual Slope A/D Type MCU with LCD

HT46R74D-1

Integrated RC or crystal oscillator

Power-down and wake-up functions reduce power

consumption

Internal 3.3V Voltage regulator and charge pump

Embedded voltage reference generator - 1.5V

6-level subroutine nesting

Bit manipulation instruction

15-bit table read instruction

Up to 0.5ms instruction cycle with 8MHz system clock

at V

=5V

63 powerful instructions

All instructions in 1 or 2 machine cycles

Low voltage reset/detector function

56-pin SSOP package

converter, LCD display, HALT and wake-up functions,

watchdog timer, as well as low cost, enhance the versa-

tility of these devices to suit for a wide range of AD with

LCD application possibilities such as sensor signal pro-

cessing, scales, consumer products, subsystem con-

trollers, etc.

January 10, 2008

Table of Contents

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Summary of Contents for Holtek HT46R74D-1

Page 1 56-pin SSOP package · External 32768Hz RTC oscillator General Description The HT46R74D-1 is an 8-bit high performance, RISC converter, LCD display, HALT and wake-up functions, architecture microcontroller device specifically de- watchdog timer, as well as low cost, enhance the versa-...
Page 2: Block Diagram
HT46R74D-1 Block Diagram Pin Assignment H T 4 6 R 7 4 D - 1 5 6 S S O P - A Rev. 1.40 January 10, 2008...
Page 3: Pin Description
HT46R74D-1 Pin Description Pin Name Options Description PA0/BZ PA1/BZ Bidirectional 8-bit input/output port. Each individual pin on this port can Wake-up be configured as a wake-up input by a configuration option. Software in- PA3/PFD Pull-high structions determine if the pin is a CMOS output or Schmitt trigger input.
Page 4: Absolute Maximum Ratings
HT46R74D-1 Absolute Maximum Ratings -0.3V to V Supply Voltage ......V +6.0V Storage Temperature ......-50°C to 125°C -0.3V to V Input Voltage......V +0.3V Operating Temperature......-40°C to 85°C Total ..............150mA Total............-100mA Total Power Dissipation ........500mW Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may cause substantial damage to the device.
Page 5 HT46R74D-1 Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions Input Low Voltage for I/O Ports, ¾ ¾ ¾ 0.3V TMR and INT Input High Voltage for I/O Ports, ¾ ¾ ¾ 0.7V TMR and INT ¾ ¾ ¾ 0.4V Input Low Voltage (RES) ¾...
Page 6 HT46R74D-1 A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ ¾ System Clock (RC OSC) 2.2V~5.5V 4000 ¾ ¾ 2.2V~5.5V 4000 System Clock (Crystal OSC) ¾ ¾ 3.3V~5.5V 8000 ¾ ¾ ¾ Internal RC OSC INRC ¾...
Page 7: Functional Description
HT46R74D-1 Functional Description Execution Flow After accessing a program memory word to fetch an in- struction code, the value of the PC is incremented by 1. The system clock is derived from either a crystal or an The PC then points to the memory word containing the external RC oscillator.
Page 8 HT46R74D-1 · Location 00CH When a control transfer takes place, an additional Location 00CH is reserved for the Timer/Event Coun- dummy cycle is required. ter 0 interrupt service program. If a timer interrupt re- sults from a Timer/Event Counter 0 overflow, and if the...
Page 9 HT46R74D-1 start of a subroutine call or an interrupt acknowledg- ment, the contents of the program counter is pushed onto the stack. At the end of the subroutine or interrupt routine, indicated by a return instruction, RET or RETI, the contents of the program counter is restored to its previous value from the stack.
Page 10 HT46R74D-1 · Branch decision (SZ, SNZ, SIZ, SDZ etc.) request flag will be recorded. If a certain interrupt re- quires servicing within the service routine, the EMI bit The ALU not only saves the results of a data operation and the corresponding bit of INTC0 or INTC1 may be but also changes the status register.
Page 11 HT46R74D-1 manner but its related interrupt request flag is T1F, Interrupts occurring in the interval between the rising which is bit 4 of INTC1, and its subroutine call location is edges of two consecutive T2 pulses are serviced on the 10H.
Page 12 HT46R74D-1 Oscillator Configuration when the system enters the power down mode, the sys- tem clock stops, the WDT oscillator keeps running with The device provides three oscillator circuits for system a period of approximately 65ms at 5V. The WDT oscilla- clocks, i.e., RC oscillator, crystal oscillator and a...
Page 13 HT46R74D-1 Watchdog Timer variations. By using the related WDT configuration op- only the PC and SP are reset to zero. There are three tion, longer time-out periods can be .implemented. If the methods to clear the contents of the WDT, an external low level on RES, a software instruction or a ²HALT²...
Page 14 HT46R74D-1 Multi-function Timer The device provides a multi-function timer for the RTC, LCD and buzzer functions but with different time-out pe- riods. The multi-function timer consists of an 8-stage di- vider and a 7-bit prescaler, with the clock source coming...
Page 15 HT46R74D-1 If the configuration options have selected that only the pin to function as an input, then this will override the con- PA0 pin is to function as a BZ buzzer pin, then the PA1 figuration option selection and force the pin to always pin can be used as a normal I/O pin.
Page 16 HT46R74D-1 Power Down Operation - HALT stimulus, the program will resume execution at the next instruction. However, if awakening from an inter- The Power-down mode is initialised by a ²HALT² instruc- rupt, two sequences may occur. If the related inter- tion and results in the following.
Page 17 HT46R74D-1 Reset There are three ways in which a reset may occur. · RES is reset during a normal operation · RES is reset during Power-down · WDT time-out is reset during normal operation The WDT time-out during a HALT or IDLE differs from other reset conditions, as it performs a ²warm reset²...
Page 18 HT46R74D-1 The register states are summarised below: Reset WDT Time-out RES Reset RES Reset WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (HALT) (HALT)* -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu -xxx xxxx -uuu uuuu -uuu uuuu...
Page 19 HT46R74D-1 Timer/Event Counter TMR1HH to the destination and latch the TMR1H and TMR1L counters to the lower-order byte buffers, re- Two timer/event counters are integrated within the spectively. Reading the TMR1H and TMR1L registers microcontroller. The Timer/Event Counter 0 contains a will read the contents of the lower-order byte buffers.
Page 20 HT46R74D-1 Bit No. Label Function To define the prescaler stages. T0PSC2, T0PSC1, T0PSC0= 000: f 001: f T0PSC0 010: f T0PSC1 011: f T0PSC2 100: f 101: f 110: f 111: f /128 Defines the timer/event counter TMR0 pin active edge: In the Event Counter Mode - T0M1,T0M0 = 0,1: 1:count on falling edge;...
Page 21 HT46R74D-1 If PA3 is selected to be a PFD output, there are two After a device reset, these input/output lines will default types of selections. One is to use PFD0 as the PFD out- to inputs and remain at a high level or in a floating state, put, the other is to use PFD1 as the PFD output.
Page 22 HT46R74D-1 Input/Output Ports Charge Pump and Voltage Regulator Additionally, the device also includes a band gap voltage generator for the 1.5V low temperature sensitive refer- A charge pump and voltage regulator are integrated ence voltage. This reference voltage is used as the zero within the device.
Page 23 HT46R74D-1 Bit No. Label Function Enable/disable Regulator/Charge-Pump module. (1=enable; 0=disable) REGCEN Charge Pump Enable/disable setting. (1=enable; 0=disable) CHPEN Note: this bit will be ignored if the REGCEN bit is disabled Bandgap quick start-up function 0: R short, quick start up...
Page 24 HT46R74D-1 Note: The V signals can come from different R groups which are selected by software registers. regulator is enabled, and also be disabled when the reg- The amplifier and buffer combination, form a differential ulator is disabled. The application program should en-...
Page 25 HT46R74D-1 state and store the time taken, Tc, which is the de-inte- In user applications, it is required to choose the correct grating time. The following formula 1 can then be used value of R and C to determine the Ti value, to allow...
Page 26 HT46R74D-1 Bit No. Label Function Defines the chopper clock. ADCCKEN should be enabled. The suggested clock value should be around 10kHz. The chopper clock definitions are: 0: clock= (f /32)/1 ADCD0 1: clock= (f /32)/2 2: clock= (f /32)/4 ADCD1...
Page 27 HT46R74D-1 LCD Display Memory The LCD clock source frequency should be chosen to be as close as possible to 4kHz. The device provides an area of embedded data memory for the LCD display. This area is located at 40H to 4FH in Note that the LCD frequency is controlled by configura- Bank 1 of the Data Memory.
Page 28 HT46R74D-1 LCD Driver Output (1/4 Duty) selected, a capacitor mounted between C1 and C2 pins is needed. The LCD driver bias voltage can be 1/2 bias or 1/3 bias by option. If 1/2 bias is selected, a capacitor mounted between V2 pin and ground is required. If 1/3 bias is se- lected, two capacitors are needed for V1 and V2 pins.
Page 29 HT46R74D-1 Low Voltage Reset/Detector Functions When the LVD function configuration option is set to the enable state, the LVD voltage option will decide the de- There is a low voltage detector, LVD, and a low voltage tecting voltage. When the LVD configuration option is r e s e t c i r c u i t , LV R , i m p l e m e n t e d w i t h i n t h e set to LVR+0.2, the actual LVD voltage depends upon...
Page 30 HT46R74D-1 Options The following shows the options in the device. All these options should be defined in order to ensure a proper function- ing system. Options OSC type selection. There are two types selection: Crystal OSC or RC OSC System clock selection: OSC or RTC clock source.
Page 31: Application Circuits
HT46R74D-1 Application Circuits S e e r i g h t s i d e R C S y s t e m O s c i l l a t o r C r y s t a l S y s t e m...
Page 32: Instruction Set
For easier understanding of the various instruction The standard logical operations such as AND, OR, XOR codes, they have been subdivided into several func- and CPL all have their own instruction within the Holtek tional groupings. microcontroller instruction set. As with the case of most...
Page 33 In addition to the above functional instructions, a range of other instructions also exist such as the ²HALT² in- ory is an extremely flexible feature of all Holtek microcontrollers. This feature is especially useful for struction for Power-down operations and instructions to...
Page 34 HT46R74D-1 Mnemonic Description Cycles Flag Affected Rotate RRA [m] Rotate Data Memory right with result in ACC None Note RR [m] Rotate Data Memory right None RRCA [m] Rotate Data Memory right through Carry with result in ACC Note RRC [m]...
Page 35: Instruction Definition
HT46R74D-1 Instruction Definition ADC A,[m] Add Data Memory to ACC with Carry Description The contents of the specified Data Memory, Accumulator and the carry flag are added. The result is stored in the Accumulator. ACC ¬ ACC + [m] + C...
Page 36 HT46R74D-1 CALL addr Subroutine call Description Unconditionally calls a subroutine at the specified address. The Program Counter then in- crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. The specified address is then loaded and the program continues execution from this new address.
Page 37 HT46R74D-1 CPL [m] Complement Data Memory Description Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice versa. [m] ¬ [m] Operation Affected flag(s) CPLA [m]...
Page 38 HT46R74D-1 INC [m] Increment Data Memory Description Data in the specified Data Memory is incremented by 1. [m] ¬ [m] + 1 Operation Affected flag(s) INCA [m] Increment Data Memory with result in ACC Description Data in the specified Data Memory is incremented by 1. The result is stored in the Accumu- lator.
Page 39 HT46R74D-1 OR A,x Logical OR immediate data to ACC Description Data in the Accumulator and the specified immediate data perform a bitwise logical OR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²OR² x Operation Affected flag(s)
Page 40 HT46R74D-1 RLC [m] Rotate Data Memory left through Carry Description The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces the Carry bit and the original carry flag is rotated into bit 0.
Page 41 HT46R74D-1 SBC A,[m] Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are sub- tracted from the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Page 42 HT46R74D-1 SIZ [m] Skip if increment Data Memory is 0 Description The contents of the specified Data Memory are first incremented by 1. If the result is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction.
Page 43 HT46R74D-1 SWAP [m] Swap nibbles of Data Memory Description The low-order and high-order nibbles of the specified Data Memory are interchanged. [m].3~[m].0 « [m].7 ~ [m].4 Operation Affected flag(s) None SWAPA [m] Swap nibbles of Data Memory with result in ACC Description The low-order and high-order nibbles of the specified Data Memory are interchanged.
Page 44 HT46R74D-1 XOR A,[m] Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR op- eration. The result is stored in the Accumulator. ACC ¬ ACC ²XOR² [m] Operation Affected flag(s)
Page 45: Package Information
HT46R74D-1 Package Information 56-pin SSOP (300mil) Outline Dimensions Dimensions in mil Symbol Min. Nom. Max. ¾ ¾ ¾ ¾ C¢ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 0° 8° Rev. 1.40 January 10, 2008...
Page 46 Copyright Ó 2008 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used...

Holtek HT46R74D-1 Technical Document

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