Lvd Operation - Holtek HT45F23A Manual

LVDC Register
Bit 7
Name —
R/W —
POR —
Bit 7~6 unimplemented, read as "0"
LVDO: LVD Output Flag
Bit 5
0: no Low Voltage Detect
1: low Voltage Detect
Bit 4 LVDEN: Low Voltage Detector Control
0: disable
1: enable
Bit 3 unimplemented, read as "0"
LVD2~LVD0: Select LVD Voltage
Bit 2~0
000: 2.0V
001: 2.2V
010: 2.4V
011: 2.7V
100: 3.0V
101: 3.3V
110: 3.6V
111: 4.4V

LVD Operation

The Low Voltage Detector function operates by comparing the power supply voltage, V
pre-specified voltage level stored in the LVDC register. This has a range of between 2.0V and 4.4V.
When the power supply voltage, V
set high indicating a low power supply voltage condition. The Low Voltage Detector function is
supplied by a reference voltage which will be automatically enabled. When the devices are powered
down the low voltage detector will remain active if the LVDEN bit is high. After enabling the Low
Voltage Detector, a time delay t
LVDO bit. Note also that as the V
of V , there may be multiple bit L
LVD
The Low Voltage Detector also has its own interrupt which is contained within one of the Multi-
function interrupts, providing an alternative means of low voltage detection, in addition to polling
the LVDO bit. The interrupt will only be generated after a delay of t
set high by a low voltage condition. When the devices are powered down the Low Voltage Detector
will remain active if the LVDEN bit is high. In this case, the LVDF interrupt request flag will be
set, causing an interrupt to be generated if V
the devices to wake-up from the SLEEP or IDLE Mode, however if the Low Voltage Detector wake
up function is not required then the LVDF flag should be first set high before the devices enters the
SLEEP or IDLE Mode.
Rev. 1.40
TinyPower Flash MCU with OPA & Comparators
TM
6 5 4
— LVDO LVDEN
— R R/W
— 0 0
, falls below this pre-determined value, the LVDO bit will be
DD
should be allowed for the circuitry to stabilise before reading the
LVDS
voltage may rise and fall rather slowly, at the voltage nears that
DD
transitions.
VDO
falls below the preset LVD voltage. This will cause
DD
V D D
V
L V D
L V D E N
L V D O
t
L V D S
LVD Operation
134
HT45F23A/HT45F24A
3 2 1
— VLVD2 VLVD1
— R/W R/W
— 0 0
DD
after the LVDO bit has been
LVD
March 29, 2019
0
VLVD0
R/W
0
, with a